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? 2005 quicklogic corporation www.quicklogic.com ? preliminary 1 ? device highlights cpu core 32-bit mips 4kc processor runs up to 200 mhz (260 dhrystone mips) 1.3 dhrystone mips per mhz mdu supports mac instructions for dsp functions 16 kb of instruction cache (4-way set associative) 16 kb of data cache (4-way set associative), lockable on a per line basis sdram memory controller support for pc-100 type sdrams, up to 256 mb total two chip selects operates at up to one-half cpu pipeline speed support for x16 and x32 external memory bus configurations i/o peripheral controller direct support for sram, eprom and flash 8-bit, 16-bit and 32-bit device widths supported eight independen t chip selects pci controller 32-bit v2.2 compatible up to 66 mhz operation supports host and satellite configurations dedicated dma channels for transmit and receive bus transactions support for external bus master arbitration (through fpga library provided by quicklogic) two ethernet controllers two 10/100 macs provides mii connection to external transceivers/devices two uarts one with modem control signals both with irda-compliant signals four general purpose 16-bit timer/counters 16-bit prescaler to increase timer/counter delay four modes of operation: decrement, increment, interval, and pulse width modulation (pwm) operation from the system bus clock or a clock source supplied from the programmable fabric system sram 16 kb accessible by all system bus masters or the programmable fabric figure 1: ql902m block diagram 32-bit system bus (amba) vialink programmable fabric low speed peripherals memory controller pci controller uart (x2) 16-bit timer (x4) icu sdram 32-bit mips 4kc 16k sram ahb master apb slave (3) 16k d-cache 16k i-cache 36 ram blocks (128x18 and 256x9) 18 ecu blocks (8x8 multiply, 16-bit carry/add) ahb slave 10/100 ethernet 10/100 ethernet mii mii sram pci 32/66 quickmips embedded standard product (esp) family ql902m quickmips? data sheet
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 2 high performance 32-bit system bus (amba bus) operates at one-half, one-third, or one-fourth of cpu pipeline speed one 32-bit ahb master port/one 32-bit ahb slave port to programmable fabric three 32-bit apb slave ports in the programmable fabric flexible programmable fabric 2016 logic cells (533 k system gates) 152 i/o pins 1.95 v vcc, 1.8/2.5/3.3 v drive capable i/o 4,284 dedicated flip-flops ieee 1149.1 boundary scan testing compliant dual-port sram modules thirty-six 2,304 bit dual-port high performance sram blocks 82,944 embedded ram bits ram/rom/fifo wizard for automatic configuration configurable and cascadable programmable i/o high performance i/o cell with fast clock-to-out time programmable slew rate control programmable i/o standards: ! lvttl, lvcmos, lvcmos18, pci, gtl+, sstl2, and sstl3 ! independent i/o banks capable of support ing multiple standards in one device ! i/o register configurations: in put, output, output enable (oe) advanced clock network multiple dedicated low skew clock networks high drive input-only networks quadrant-based segm entable clock networks user-programmable phase lo cked loop (pll) circuit embedded computational units (ecus) eighteen hardwired dsp building blocks with inte grated multiply, add, and accumulate functions.
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 3 security features the quicklogic products come with secure vialink ? technology that protects intellectual property from design theft and reverse engineering. no external conf iguration memory is needed for the fabric. the device is instant-on at power-up. quickworks design software the quickworks ? package provides the most complete esp and field programmable gate array (fpga) software solution from design entry to logic synthesi s, to place and route, and simulation. the package provides a solution for designers w ho use third party tools from cadence, mentor, synopsys, and other third- party tools for design entry, synthesis, or simulation. process data the ql902m is fabricated on a 0.18 , six layer metal cmos process. the core voltage is 1.95 v v cc supply and the i/os are up to 3. 3 v compliant. the ql902m is available in commercial and industrial temperature grades.
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 4 ql902m architectural overview the ql902m chip can be thought of as having two distinct sides , an application specific standard product (assp) side and a programmable fabric side. the assp side contains the standard cell circuitry of the device such as the mips 4kc cpu and the ethernet macs, an d the fabric side contains all of the programmable logic elements (e.g., logic cells and dual-port rams) of the device. assp side this section discusses the va rious circuits in the assp portion of the ql902m device. cpu core the mips32 4kc processor core is a hi gh-performance, low-power, 32-bit mi ps risc core capable of speeds up to 200 mhz. the 4kc core contai ns a fully-associative translation lookaside buffer (t lb) based memory management unit (mmu) and a pipelined mdu. the core executes the mips32 instructio n set architecture (isa). it supports all application co de in the mips i, ii, iii, and iv instruction sets. it also supports kernel code for the r4000 processor and above. the mips32 isa contains special multiply-accumulate, conditional mo ve, prefetch, wait, and zero/one detect instructions. the mmu contains a three-entry instruction tlb (itlb), a three-entry data tlb (dtlb), and a 16 dual-entry joint tlb (jtlb) with variable page sizes. the 4kc multiply-divide unit (mdu) supports a maximum issu e rate of one 32x16 multiply (mul/mult/multu), multiply-add (madd/maddu), or multiply-subtract (msub/msubu) operation per clock, or one 32x32 mul, madd, or msub every other clock. instruction and data caches the instruction and data caches are both 16 kbytes in size. each cache is organized as four-way set associative. the data cache has lockout capability per cache line. on a cache miss, loads are blocked only until the first critical word becomes available. the pipeline resume s execution while the remaining words are being written to the cache. both caches are virtually indexed and phys ically tagged. virtual indexing allows the cache to be indexed in the same clock in which the address is gene rated rather than waiting fo r the virtual-to physical address translation in the mmu. ejtag interface the basic enhanced jtag (ejtag) features provide cpu run control with stop, single stepping and re-start, and software breakpoints through the sdbbp instruction. in addition, instruction and data virtual address hardware breakpoints, and connection to an external ejtag probe through the test access port (tap) is included.
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 5 assp pll on the assp side of the ql902m there is a single cloc k input that provides an in put clock reference for the mips core, the system bus, and all assp peripherals (o ther than the pci controll er, which is independently driven by the pci_clk input). this clock input (cpu_pll_ clkin) is the input to a pll that is fixed at an 8 times clock multiplication rate. for example, if the clock rate applied to cpu_pll_clkin is 25 mhz, the resultant clock that drives the mips core is 200 mhz. table 1 shows the maximum input clock rates for cpu_pll_clkin based upon the assp sp eed grade of the given ql902m device. the system bus clock can run at a maximum rate of one -half the mips core clock frequency. other ratios (one-third and one-fourth) are also possible and cont rolled by the cpu_pll_di v(1) and cpu_pll_div(0) inputs as shown in table 2 . sdram memory controller the ql902m sdram memory controller (sdmc) provides all the necessary logic to connect to a wide variety of industry standard sdrams for use by th e cpu, ethernet controllers, pci controller, and programmable fabric. the sdmc supports a minimu m sdram size of 16 mbytes and a maximum sdram size of 256 mbytes. the sdram controller controls the sdram on the extern al bus. on receiving an access request, the sdram controller decides on the appropriate commands to send to the sdram memory. the dram bank controller sequences all of the command s required to complete a read or write request to an sdram memory location with timing controlled by the cas delay and ras delay values. the bus interface is a slave on the system bus; it co ntains the control register block. the bus interface produces read, write, refresh and mode register write requests to the sdram control engine, and software supplied configuration information. table 1: maximum input frequency for cpu_pll_clkin and mips core frequency based on ql902m assp speed grade quickmips device part number prefix maximum input frequency for cpu_pll_clkin resultant maximum mips core frequency ql902m175 21.875 mhz 175 mhz ql902m200 25.000 mhz 200 mhz table 2: mips core clock rate to system bus clock rate (hclk) ratio based on cpu_pll_div(1) and cpu_pll_div(0) signals cpu_pll_div(1) cpu_pll_div(0) ratio mips core clock rate : system bus clock rate (hclk) system bus clock (hclk) duty cycle 0 x 2:1 50% 1 1 3:1 33% a a. in 3:1 mode, the system bus clock duty cycle is not symmetric. this affect s the internal system bus clock as well as hclk and the sdram clock source (sd_clkout). therefore, care must be taken so that minimum clock pulse widths are not violated when these clock signals are used to drive externally connected devices. 1 0 4:1 50%
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 6 data is transferred to and from the sdram as unbroken quad words. this data packet size is convenient for cache line fills and buffered writes. for accesses smaller than a quad word, extra read data is ignored by the sdram controller; for writes, the sd_dqm(3:0) pins ar e used to force the sdrams to ignore invalid data. for access sizes larger than a quad word, multiple quad word accesses are issued to the sdram control engine. i/o peripheral controller this section describes access to i/o and memory devices on the external m bus (with the exception of sdram). the i/o peripheral controller ( figure 2 ) generates strobes and signals th at can be used to interface the m bus with common asynchronous peripheral devices. the ql902m peripheral controller unit (pcu) provides de coded strobe signals to c ontrol external peripherals such as sram, flash, real time clock (rtc) and memo ry mapped i/o devices. it supports 8-bit, 16-bit, and 32-bit widths with programmable wait states and bu s turnaround time based on memory speed. the pcu provides the following functionality: decoding of memory access in the local cpus memory map to generate chip selects or strobes. control of wait states for decoded regions. a total of eight chip select signals are available. chip select seven is used as the boot rom chip select. the m bus is a shared resource between the sdram controller and i/o controller. the m bus is assigned to one of these two controllers by an internal arbiter. there is one turn-around cycle when switching from one controller to the other. figure 2: sdram and i/o controllers i/o controller m bus controller addr[23:0] data[31:0] bls[3:0] oe we cs[7:0] sdram controller sd_dqm[3:0] sd_cs[1:0] sd_ras sd_cas sd_we sd_cke[1:0] sd_clkout sd_clkin addr[14:0] data[31:0] mux addr[23:0] data[31:0] m bus system bus
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 7 pci controller the quickmips pci interface is a 32-bit, 66 mhz, revisi on 2.2 compliant interface as specified by the pci local bus specification. this section provides a detail ed description of the pci controller functionality. figure 3 shows a simplified block diagram of the pci contro ller. the pci controller is a bridge between the on-chip system bus and the external pci bus. there ar e two main modes of operation of the pci function, each utilizing several resources: pci target ! pci target access to system address space ! pci target to pci configuration registers ! pci target to extended regi sters (dma and message/mailbox) pci master ! system address space to pci access ! system-to-pci and pci-to-system dma ! pci master read/write generated th rough the single access register figure 3: pci block diagram pci interface system bus target interface master interface pci master pci target pci configuration registers dma registers 32 pci bus read fifo (32x32) write fifo (32x32) single access registers read fifo (8x32) write fifo (8x32) dma controller message unit
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 8 the pci controller can be used as a system host or as a secondary master: system host: the ql902m pci interface is connected to the root pci bus segment (bus 0) and the on- chip cpu performs bus enumeration to determine how all pci base address registers are configured. the sdram controlled by the ql902m is used as the main memory. ! the single access controller can be used for perf orming enumeration upon system boot, and then to perform i/o operations to i/o mapped pci devices. ! the system bus to pci memory aperture can be us ed by host drivers to control memory mapped pci devices (pio). ! the dma controller provides the most efficient way to transfer large blocks of data between system memory and external pci target devices (such as video controllers, etc.). secondary master: the ql902m is enumer ated by an extern al pci host cpu. ! the pci configuration registers of the ql902m ar e recognized by the host cpu and enumerated accordingly. ! the dma controller can be used to efficiently move data between local ql902m-controlled sdram and the host memory. ! the single access controller can be used to tran sfer small amounts of data in and out of the host memory space. ! the message unit can be used as an inter-cp u communication mechanism for a host driver to synchronize with a local driver running on the ql902m cpu. ! the pci to local system bus aperture can be used to allow the host cpu or other pci agent to access ql902m memory directly.
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 9 ethernet controllers the ql902m has two ethernet media access controll ers (macs) embedded in th e assp portion of the device. the ethernet controllers incorporate the essential protocol requirements for operation of ethernet/ieee 802.3 compliant nodes, and provide interfaces between the host subsystem and the media independent interface (mii). each 10/100 mac can operate in 10 mbps or 100 mbps mode based on the transmit and receive clocks provided (2.5/25 mhz). th e controllers contain transmit and receive fifos and embedded dma control. figure 4 shows a block diagram of th e ql902m ethernet controller. figure 4: ethernet controller block diagram the dma controller is responsible for exchanging data between the fifos and the system memory. dma operation is controllable through a set of control and status registers. each 10/100 mac operates in half-duplex mode and full -duplex modes. when operating in the half-duplex mode, the 10/100 mac core is fully compliant to se ction 4 of iso/iec 8802-3 (ansi/ieee standard) and ansi/ieee 802.3. when operat ing in the full-duplex mode, the 10/100 mac core is compliant to the ieee 802.3x standard for full-duplex operations. each 10/ 100 mac is also compatible with home pna 1.1. the 10/100 mac core provides programm able enhanced features designed to minimize host supervision, bus utilization, and pre- or post-message processing. these features include the ability to disable retires after a collision, dynamic fcs generation on a frame-by-frame ba sis, automatic pad field insertion and deletion to enforce minimum frame size attributes, automatic retransmission and detection of collision frames. the 10/100 mac core can sustain transmis sion or reception of minimal-sized back-to-back packets at full line speed with an inter-packet gap (ipg) of 9.6 s for 10-mb/s and 0.96 s for 100-mb/s. data to/from the mac is buffered in transmit/receive fi fos. in the case of data received by the ethernet mac, the data is drained from the receive fifo by the dma controller and stored to the specified target (typically the data is stored in sdram). for ethernet transmit, the dma controller reads data from memory (sdram typically) and pushes it into the transmit fifo . dma operation is controllable through a set of control and status registers. with the exception of the m1_rxclk, m2_rxclk, m1 _txclk and m2_txclk signals, the mii interface is located on the assp/fabric boundary internal to the de vice. if the designer wants to use one or both of the ethernet macs, the signal ports on this interface must be brought out to fabric io pins in the top-level fabric design. table 3 shows the recommended fabric io pin locations for the mii interface pins. system bus mii dma controller tx fifo rx fifo fabric 10/100 mac
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 10 table 3: mii interface signals and recommended fabric io pin locations mii interface signal mii interface direction a a. mii interface direction is specified with respect to the assp porti on of the device. i design ates an input to the assp and o designates an output from the assp. fabric pin signal fabric pin type fabric pin location m1_col i m1_col i f1 m1_crs i m1_crs i g2 m1_mdc o m1_mdc o f3 m1_mdi i m1_mdio b i/o/z k4 m1_mdo o m1_mdo_en_n o m1_rxd(0) i m1_rxd(0) i f2 m1_rxd(1) i m1_rxd(1) i e1 m1_rxd(2) i m1_rxd(2) i e2 m1_rxd(3) i m1_rxd(3) i d1 m1_rxdv i m1_rxdv i l4 m1_rxer i m1_rxer i d2 m1_txd(0) o m1_txd(0) o l3 m1_txd(1) o m1_txd(1) o c1 m1_txd(2) o m1_txd(2) o l5 m1_txd(3) o m1_txd(3) o b1 m1_txen o m1_txen o e3 m2_col i m2_col i k22 m2_crs i m2_crs i l24 m2_mdc o m2_mdc o c25 m2_mdi i m2_mdio b b. the m1_mdio and m2_mdio signals require th e instantiation of a bipad_25um macro. see figure 5 for more details. i/o/z e25 m2_mdo o m2_mdo_en_n o m2_rxd(0) i m2_rxd(0) i b26 m2_rxd(1) i m2_rxd(1) i l23 m2_rxd(2) i m2_rxd(2) i e24 m2_rxd(3) i m2_rxd(3) i c24 m2_rxdv i m2_rxdv i f24 m2_rxer i m2_rxer i l22 m2_txd(0) o m2_txd(0) o m24 m2_txd(1) o m2_txd(1) o c26 m2_txd(2) o m2_txd(2) o m23 m2_txd(3) o m2_txd(3) o d26 m2_txen o m2_txen o m22
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 11 the pin assignments in table 3 represent connections to io banks a and d of the fabric. if the ethernet macs are connected in this fashion, these two banks must be configured for 3.3 v operation. see table 17 for more details. as table 3 indicates, the mn_mdio pin is bi-directional. th e signal on this pin is made up of three mii interface signals. mn_mdi and mn_mdo are the da ta input and output signals respectively, and mn_mdo_en_n is the tri-state buffer enable signal th at turns on the pin output driver. mn_mdo_en_n is active low, and must be made active high by running it through a logic cell inverter before connecting it to the bipad_25um macro. figure 5 shows how these connections are made to the bipad_25um macro. figure 5: bipad_25um macro and connections to mii interface signals the remainder of the mii signals are simple inputs or outputs and can be connected to the fabric io pins directly without the instantiation of any specific macros. system sram the ql902m contains 16 k bytes of sram internal to th e assp portion of the device. this sram is divided into four equal sections of 4 kb each (each arra nged as 32-bit x 1024 words), and each section can be configured to be connected to the system bus (speci fically, ahb) or connected to the fabric directly. when connected to the ahb, the sram (an ahb slave) can be accessed by any ahb master. furthermore, the 4kc core can use this internal sram for data or instruction storage. the sram supports 32-bit, 16-bit, or single byte accesses. when connected to the fabric, the sram can be accessed directly by any fabric design without suffering the overhead of accessing it through the ahb interface. in addition, the fabric has a master ahb interface, which it may also use to access the sram. however, in some high-speed applications, it may be necessary for the fabric to have exclusive access to the sram memory. the fabric interface of the sram block facilitates this function, and is described below. figure 6 shows the connection scheme of the four memory banks between the fabric and the ahb. en a p q connect to inverted copy o f mn_mdo_en_n connect to mn_mdo connect to mn_mdi mn_mdio
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 12 figure 6: sram connection scheme between the fabric and ahb each sram block is single ported, and is connected to the fabric or ahb through a selection mux. for each sram block, the address bus, control si gnals, clock, and data write bus are all multiplexed by a register bit that is accessible through the system bu s. therefore, any ahb master may control the switch of a given sram block between the ahb and the fabric interface. because each sram clock is also switch ed by the selection mux, it is po ssible for the fabric to drive each sram block with a separate clock. however, when an sram block is connected to the ahb interface, the system bus clock (hclk) is always used to drive the block. refer to table 51 for descriptions of all the system sram signals that interface to the fabric. sram block system target interface 4k sram (1024x32) read data 32 gl_sr_select register fabric sram 1 interface address, write data, clock, and control 4k sram (1024x32) read data 32 sram 2 interface address, write data, clock, and control 4k sram (1024x32) read data sram 3 interface address, write data, clock, and control 4k sram (1024x32) read data sram 4 interface address, write data, clock and control system bus 32 32 48 48 48 48
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 13 interrupt controller this section describes the function of th e ql902m interrupt controller unit (icu). figure 7 shows a block diagram of the interrupt controller. figure 7: simplified interr upt controller block diagram the ql902m has 9 on-chip peripheral interrupts and 7 external interrupts (including on nmi), for a total of 16 interrupt sources. these 16 interrupt sources are combin ed into 7 interrupts by th e interrupt controller and fed to the cpu core. external interrupts must be asserted for at least two clock periods in orde r to be recognized as an interrupt. all interrupts are level triggered. each interrupt has an emulation enab le register bit and an emulation interrupt value register bit in the interrupt controller. the primary use for the emulation re gisters is for testing purposes. the interrupt enable bits are stored in the gl_emul_en register. the emulati on interrupt value for each po ssible interrupt is stored in the gl_int_emul register. each interrupt has an enable bit in the global indivi dual interrupt enable (gl_ind_int_en) register in the interrupt controller. each interrupt also has a status bit in the gl obal individual interrupt status (gl_ind_int_status) register in the interrupt controller. the global cpu interrupt enable register (gl_cpu_in t_en) enables masking of th e interrupt groups after they have been grouped together. the interrupt controller has no programma bility for priority. that is, there is no hardware priority encoder. priority is provided as a function of software. system bus mips 4kc cpu core global logic (gl) pll and clock divider (pl) interrupts to cpu interrupts from on-chip peripherals/fabric configuration options clocks and reset
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 14 high performance 32-bit system bus (amba bus) the purpose of this section is to describe the amba 1 bus operation for the purpos es of implementing user circuits in the programmable fabric. all circuits in the assp portion of the ql902m chip communicate with the programmable fabric primarily through the amba bus interfaces (advan ced microcontroller bus architecture from arm). circuits implemented in the pr ogrammable fabric must be designed according to the amba specification, revision 2.0. the devices with in the ql902m are interconnect ed through the advanced high-performance bus (ahb) or the advanced peripheral bus (apb). re fer to the amba specification, revision 2.0, for more detailed information about the ahb and apb. advanced high-performance bus (ahb) the ahb is the high-performance variant of the amba specification. it supports multiple bus masters and provides high bandwidth operation. the ahb implemen tation in the ql902m is 32 bits wide. all signals are synchronous to the rising clock edge of the bus clock (hclk). the key features of the ql902m ahb include: burst transfers single-cycle bu s master handover 32-bit bus runs at up to half the cpu clock frequency multiple bus masters arbitration through an ahb arbiter address decoding through an ahb decoder table 4 lists the master and slave devices that connect to the ahb. the ql902m ahb supports multiple bu s masters as well as bus slaves. on ly one bus master can use the bus at a given time. the bus master provides address and control information when performing read and write operations. in response to the read or write operation from the bus master within a given address range, a bus slave provides information regarding the status of the data transfer (success, failure, or wait). the ahb arbiter ensures that only one bus master is initiating data transfers. the ahb decoder decodes the address of each transfer and provides a select signal for the slave that is involved in the transfer. 1. amba is a trademark of arm ltd. table 4: master and slave devices on the ahb ahb masters ahb slaves mips 4kc cpu system sram pci pci ethernet controller 1 ethernet controller 1 ethernet controller 2 ethernet controller 2 32-bit master interfac e to programmable fabric 32-bit slave interface to programmable fabric sdram and i/o peripheral controllers interrupt controller ahb to apb bridge
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 15 ahb arbitration the internal arbiter of the ql902m provides either fixed arbitration priority or round robin rotating priority. preemption occurs only after a burst of four. consequently, when a low priority master is in control of the bus and a higher priority master requests access, the lower prio rity device will lose its grant after a burst of four before another master takes control. this minimizes the loss of performance that happens when bursts are preempted. this preemption only happens when the designated ahb ma ster is performing bursts of undefined lengths. if the ahb master is performing a burst of a defined (fi xed) length, the burst will complete without interruption by the arbiter. the arb_fair_en bit in the gl_int_emul re gister determines the priority scheme. when fixed priority is chosen, the priority of ahb masters is as follows (highest to lowest): 1. mips 4kc cpu 2. ethernet controller 1 3. ethernet controller 2 4. pci controller 5. programmable fabric advanced peripheral bus (apb) the apb is a simplified bus that is ideal for implementing device control registers and other non-burst transfers. the apb is a 32-bit wide bus that runs at the same frequency as ahb. the apb only accommodates slaves, does not support burst transfers, and does not support advanced slave resp onse operations such as retries or wait state insertion. the apb on th e ql902m is supported through an ah b-to-apb bridge. three separately decoded apb regions are available for apb devices implemented in the fabric. table 5 lists the slave devices on the apb. table 5: slave devices on the apb apb slaves two uarts four 16-bit timers/counters three 32-bit slave interfaces to programmable fabric
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 16 uarts the ql902m chip contains two uart s. each uart provides a full- duplex asynchronous receiver and transmitter and has programmable baud rates. the uart s contain an irda serial infrared (sir) encoder/ decoder (endec). one uart also has modem control si gnals. the serial output is software selectable between irda and generic serial modes. figure 8 shows a block diagram of the uart. figure 8: uart block diagram the key features of the uarts are as follows: programmable baud rate generation of up to 1/16 system bus clock rate fifo enable or disable 5, 6, 7, or 8 data bits 1 or 2 stop bits odd and even, stick or no parity parity, framing, and overrun error detection line break generation and detection loopback interrupt generation transmit fifo baud rate generator receive fifo reveiver transmitter fifo status / interrupt generation sir receive decoder sir transmit decoder tx data rx data system clock interrupt sir endec system bus interface register block
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 17 irda sir endec block providing: ! programmable use of irda sir or uart input/output ! support of irda sir endec functions for data rates up to 115.2 kilobi ts/second ha lf-duplex ! support of normal 3/16 and low-po wer (1.41 to 2.23s) bit durations ! programmable internal clock generato r allowing division of reference clock by 1 to 512 for low-power mode bit duration the system bus (apb interface) generates read and write decodes for accesses to status/control registers and transmit/receive fifo memories. the register block st ores data written or to be read across the apb interface. the baud rate generator contains free-running counters that generate a clock that is 16 times the transmit/receive bit rate. the transmit fifo is an 8-bit wide, 16-entry deep fi fo memory buffer. cpu data written across the apb interface is stored in the fifo until read out by the tr ansmit logic. the transmit fifo can be disabled to act like a one-byte holding register. the receive fifo is a 12-bit wide, 16-entry de ep fifo memory buffer. received data and corresponding error bits, are stored in the receive fifo by the receive logic until read out by the cpu across the apb interface. the receive fifo can be disabled to act like a one-byte holding register. the transmitter performs parallel-to-serial conversion on the data read from the transmit fifo. control logic outputs the serial bit stream beginning with a start bit, data bits, least significant bit (lsb), a parity bit, and then stop bits according to the programmed configurati on in control registers. the receiver performs serial- to-parallel conversion on the received bitstream after a valid start pulse has been detected. overrun, parity, frame error checking, and line break detection are also performed, and the data with associated overrun, parity, framing, and break error bits is written to the receive fifo. the interrupt generator outputs a single, combined interrupt to the ql902m interrupt controller. the sir transmit encoder modulates the non-return-to -zero (nrz) transmit bitstream output from the ql902m chip. the irda sir physical layer specifies us e of a return to zero, inverted (rzi ) modulation scheme that represents logic 0 as an infrared light puls e. the modulated output pulse stream is transmitted to an external output driver and infrared light emitting diode (led). the sir receive decoder demodulates the return-to-zero bit stream from the infrared detector and outputs the received nrz serial bitstream to the ql902m uart received data input. the decoder input is normally high (marking state) in the idle state. the transmit encoder output has the opposi te polarity to the decoder input.
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 18 general purpose 16- bit timer/counters the ql902m chip has four independent 16-bit timer/co unter modules. the configuration registers for these modules are accessible through the system bus (apb). the system bus clock (hclk), or an external clock su pplied from the fabric, driv e the clock inputs on the timer/counter modules. these counters operate in one of four modes: decrement, increment, interval, or pulse width modulation (pwm). each timer/counter module has the capability to generate system interrupts on various events. one timer/counter is configured, by default, as a watchdog ti mer after a system rese t. this watchdog timer has its own system interrupt output. figure 9 shows a functional block diagram of the timer module. figure 9: timer functional block diagram system bus 32-bit mips 4kc cpu 16k d-cache 16k i-cache tm_fbenable 7 interrupts counter 4 control registers counter 3 counter 2 counter 1 wd int timer int tm_extclk[4:1] 4 tm_enable tm_overflow 3 tm_overflow[4:2] 16-bit timer/counters tm_enable tm_overflow[1] programmable vialink fabric icu
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 19 the key features of each timer/ counter module are as follows: up to 100 mhz operation. 32-bit data path on the system bus. 16-bit timer/counter. 16-bit pre-scaler to increase timer/counter delay. four modes of operation: decrem ent, increment, interval and pwm. operation from the system bus clock (hclk) or an external clock from the fabric. two external hardware timer enable signals can be used to start/stop the timer/counter. one of these signals can be supplied from the fabric and th e other is a dedicated input pin on the chip. three match interrupts, one interval interrupt and one overflow interrupt. six control registers to control various counter functions, including enable /disable, load, and reset. the timer/counters are controlled by a set of control registers. each timer/counter module has six control registers. by contrast, one interrupt register is used to control and convey the status of the interrupts from all the modules. one counter (counter 4) is configured, by default, to be used as a watchdog timer after the system reset. this watchdog timer has its own system in terrupt output, and it can be rec onfigured by software for use as a standard timer/counter.
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 20 fabric side this section discusses the various circuit elements in the fabric portion of the ql902m device. logic cells the ql902m logic cell structure presented in figure 10 is a dual register, multiplexor-based logic cell. it is designed for wide fan-in and multip le, simultaneous output functions. both registers share clk, set, and reset inputs. the second register ha s a two-to-one multiplexer controll ing its input. the register can be loaded from the nz output or directly from a dedicated input. note: the input pp is not an ?input? in the classical sense. it is a static input to the logic cell and selects which path (nz or ps) is used as an input to the q2z register. all other inputs are dynamic and can be connected to multiple routing channels. the complete logic cell c onsists of two 6-input and gates, four two-input and gates, seven two-to-one multiplexers, and two d flip-flops with asynchronous set and reset controls. the cell has a fan-in of 30 (including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six outputs (four combinatorial and two registered). the high logic capacity and fan-in of the logic cell accommodates many user functions with a single level of logic delay while other architectures require two or more levels of delay. figure 10: ql902m logic cell a1 a2 a3 a4 a5 a6 az oz qz nz q2z fz os op b1 b2 c1 c2 mp ms dq dq d1 d2 e1 e2 np ns f1 f2 f3 f4 f5 f6 ps pp qc qr qs
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 21 dual-port sram modules the ql902m includes up to 36 dual-po rt 2,304-bit ram modules (shown in figure 11 ) for implementing ram, rom, and fifo functions. each module is user-c onfigurable into two different block organizations and can be cascaded vertically to increas e their effective depth or horizontally to increase their effective width as shown in figure 12 . figure 11: 2,304-bit ram module using two mode pins, designers can configur e each module into 128 x 18 (mode 0) or 256 x 9 (mode1). figure 12: cascaded ram modules the ram modules are dual-port, with completely independent read and write ports and separate read and write clocks. the read ports support asynchro nous and synchronous operation, while the write ports support synchronous operation. each port has 18 da ta lines and 8 address lines, allowing word lengths of up to 18 bits and address spaces of up to 256 wo rds. depending on the mode selected, however, some higher order data lines or the highest order address line may not be used. the write enable (we) line acts as a clock enable for synchronous write operation. the read enable (re) acts as a clock enable for synchronous read operation (asyncrd input low). the re and rclk inputs are ignored when asyncrd is tied high. mode[1:0] wa[7:0] wd[17:0] we asyncrd ra[7:0] rd[17:0] re 2,304-bit module wclk rclk ram module (2,304 bits) ram module (2,304 bits) rdata raddr rdata wdata waddr wdata
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 22 designers can cascade multiple ram modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. a similar technique can be used to cr eate depths greater than 256 words. in this case address signals higher than the eighth bit are encoded onto the write enab le (we) input for write operations. the read data outputs are multiplexed together us ing encoded higher read address bits for the multiplexer select signals. the ram blocks can be loaded with da ta generated internally (typically for ram or fifo functions) or with data from an external prom (typically for rom functions). dual-port sram module signals the dual-port ram module signal descriptions are shown in table 6 . table 6: dual-port ram module signal descriptions signal name i/o description wclk i write clock. clock input for the write port of the ram module. all write port input signals are synchronous with this clock. we i write enable. sampled on the rising edge of wclk, when we is high, data is written into the ram module at the specified write address. wa(7:0) i write address. sampled on the rising edge of wclk, this is the write address for the data to be written into the ram module. wa(7:0) is ignored wh en we is low. note that some higher order bits of wa(7:0) may not be used depending on the selected mode for the ram module (see mode(1:0) signal description). wd(17:0) i write data. sampled on the rising edge of wclk, this is the data to be written into the ram module. wd(17:0) is ignored when we is low. note that some higher order bits of wd(17:0) may not be used depending on the selected mode for the ram module (see mode(1:0) signal description). rclk i read clock. this is the clock input for the read port of the ram module. if asyncrd is low, all read port i/o signals are synchronous with this clock. if asyncrd is high, rclk is ignored. re i read enable. sampled on the rising edge of rclk, when re is high, data is read from the ram module at the specified read address. if asyncrd is high, this re is ignored. ra(7:0) i read address. this is the read address for data to be read from the ram module. if asyncrd is low, ra(7:0) is sampled only on the rising edge of rclk while re is high. if asyncrd is high, ra(7:0) is continuously sampled by the ram module and re has no effect. note that some higher order bits of ra(7:0) may not be used depending on the selected mode for the ram module (see mode(1:0) signal description). rd(17:0) o read data. this is the read output data from the ram module. if the ram module is in synchronous read mode (asyncrd low), valid read data is output immediately following the rising edge of rclk which sampled re as high. if the ram module is in asynchronous read mode (asyncrd high), valid read data is output immediately after any change in the read address. note that some higher order bits of rd(17:0) may not be used depending on the selected mode for the ram module (see mode(1:0) signal description). asyncrd i asynchronous read input. this signal, when high, indicates to the ram block that the read port should operate asynchronously. when low, all read port i/o signals are synchronous with rclk. this signal can only be tied to ?1? or ?0? inside the fabric. mode(1:0) i mode for ram module. these bits configure the width and depth of the ram module (for both the read and write ports) and can only be tied to ?1? or ?0? inside the fabric. the possible ram module modes are: mode(1:0) = ?00? : 128 x 18 (locations x data bits) mode(1:0) = ?01? : 256 x 9 (locations x data bits) mode(1:0) = ?1x? : reserved
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 23 embedded computati onal units (ecus) traditional programmable logic architec tures do not implement arithmetic fu nctions efficiently or effectively? these functions require high logic cell usage wh ile garnering only moderate performance results. the ql902m architecture allows for fu nctionality above and beyond that ac hievable using pr ogrammable logic devices. by embedding a dynamicall y reconfigurable computational un it, the ql902m device can address various arithmetic functions efficiently. this appr oach offers greater performance than traditional programmable logic implementations. the embedded block is implemented at the transistor level as shown in figure 13 . figure 13: ecu block diagram s3 s2 s1 d c b a cin a[15:0] clk b[15:0] sign2 sign1 a[15:8] a[7:0] reset 3-4 decoder 8-bit multiplier 16-bit adder q[16:0] dq 00 01 10
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 24 ecu signals table 7 defines the ecu i/o signals. for more informati on on the operation of the ecu, see quicklogic application note 52 at http://www.quicklogic.com /images/appnote52.pdf . table 7: ecu i/o signals signal name i/o description clk i clock input. input clock for the ecu output register. reset i reset input. active high reset input for the ecu output register. s1 i ecu control s1. one of three instruction signals t hat define the configuration mode of the ecu (see table 8 ). s2 i ecu control s2. one of three instruction signals t hat define the configuration mode of the ecu (see table 8 ). s3 i ecu control s3. one of three instruction signals t hat define the configuration mode of the ecu (see table 8 ). cin i carry input. 1-bit carry in for 16-bit adder operations. sign1 i sign input for multiplier a input. when sign1 = ?1?, a(7:0) is treated as signed or two?s complement binary. when sign1 = ?0? a(7:0) is treated as unsigned binary. sign2 i sign input for multiplier b input. when sign2 = ?1?, b(15:8) is treated as signed or two?s complement binary. when sign2 = ?0? b(15:8) is treated as unsigned binary. a(15:0) a(15:8) a(7:0) i augend input. 16-bit augend input of the 16-bit adder when the ecu is in any of the adder configuration modes. multiplicand input. 8-bit multiplicand input when the ecu is in any of the multiplier configuration modes. multiplier input. 8-bit multiplier input when the ecu is in any of the multiplier configuration modes. b(15:0) i addend input. 16-bit addend input when ecu is in any of the adder configuration modes. q(16:0) o ecu output. this is the 17-bit output of the ec u. the interpretation of the value of q(16:0) depends on the setting of s1, s2, s3, sign1, and sign2.
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 25 the ql902m ecu blocks are placed next to the sram circuitry for efficient memory/instruction fetch and addressing for dsp algorithmic implementations. up to eighteen 8-bit mac functions can be implemente d per cycle for a total of 1.8 billion macs/s when clocked at 100 mhz. additional multip ly-accumulate functions can be implem ented in the prog rammable logic. the instruction modes for the ecu block are dynamica lly re-programmable through the programmable logic as shown in table 8 . table 8: ecu mode select criteria instruction operation s1 s2 s3 0 0 0 multiply 0 0 1 multiply-add 0 1 0 accumulate 0 1 1 add 1 0 0 multiply (registered) a a. b (15:0) set to zero. 1 0 1 multiply- add (registered) 1 1 0 multiply - accumulate 1 1 1 add (registered)
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 26 fabric pll instead of requiring extra components, designers simp ly need to instantiate the ql902m fabric pll model (described in this section) . the fabric pll built into the ql902m supp orts a wider range of frequencies than many other plls. the pll also has the ability to supp ort different ranges of frequency multiplications or divisions, driving the fabric at a faster or sl ower rate than the incoming clock frequency. figure 14 illustrates the ql902m fabric pll. figure 14: ql902m fabric pll block diagram the ql902m fabric pll is driven by the fb_pll_clkin input pin. this input is used by the pll as a clock reference for the voltage controlled oscillator (vco) inte rnal to the pll circuit. using the m1 and m0 inputs to the pll block, the designer may choose a frequenc y multiplier value for the vco. the pll output pin, fb_pll_padout runs at the vco operational frequency. table 9 shows the minimum and maximum input (f in ) and output (f pad ) frequency for each possible vco multiplier mode. lock detect vco phase frequency detector fb_pll_clkin fb_pll_reset_n phase adj. phase adj. : m : fd fb_pll_padout pllclk_out pllclk_out2 fd = 1, 2, 3, 4 or 8 phase = 0, 90, 180, 270 phase = 0, 90, 180, 270 charge pump m = 2, 4 or 8 fd0 fd1 fd2 m0 m1 ps0 ps1 ps2 ps3 lock_detect
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 27 in addition to the fabric pll output pin, the pll can also drive two clock networks in the fabric. these two additional outputs, pllclk_out and pllclk_out2 offer further control over frequency and phase by adding an output frequency divider and phase adju stment control. pllclk_o ut and pllclk_out2 can be configured for different ou tput phases, but they both operate at the same frequency. table 10 shows the fabric clock network pllclk_out resultant output frequency (f fab ), duty cycle and phase based on the fd2, fd1, fd0, ps3 and ps2 inputs. note: pllclk_out phase shown in the table 10 is based on the period 1/f fab . note: an output phase of 0 indicates that the rising edge of pllclk_out will be aligned with the rising edge of fb_pll_clkin. note: to maintain the phase values shown in table 10 , f vco should not exceed 200 mhz. if f vco is set above 200 mhz, the phas e of pllclk_out will have no gua ranteed relation to fb_pll_clkin. table 9: frequency ranges for fabric pll input pad (fb_pll_clkin), output pad (fb_pll_padout) and vco m1 m0 vco mode fb_pll_clkin (f in ) input frequency range fb_pll_padout (f vco and f pad ) pad output frequency range 0 0 2x 50.0 to 150.0 mhz 100 to 300 mhz 0 1 4x 25.0 to 75.0 mhz 100 to 300 mhz 1 0 8x 12.5 to 37.5 mhz 100 to 300 mhz 1 1 reserved ? should not be used table 10: frequency, duty cycle and phase values for fabric pll output pllclk_out fabric output pllclk_out fd2 fd1 fd0 (f fab ) frequency duty cycle ps3 ps2 phase 0 0 0 f vco 50% x x 0 0 0 1 f vco / 2 50% 0 0 180 0 1 270 1 0 0 1 1 90 010f vco / 3 33% x x 0 0 1 1 f vco / 4 50% 0 0 0 0 1 90 1 0 180 1 1 270 1 x x f vco / 8 50% 0 0 270 0 1 0 1 0 90 1 1 180
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 28 table 11 shows the fabric clock network pllclk _out2 resultant output frequency (f fab ), duty cycle and phase based on the fd2, fd1, fd0, ps1 and ps0 inputs. note: pllclk_out2 phase shown in the table 11 is based on the period 1/f fab . note: an output phase of 0 indicate s that the rising edge of pllclk_o ut2 will be aligned with the rising edge of fb_pll_clkin. note: to maintain the phase values shown in table 11 , f vco should not exceed 200 mhz. if f vco is set above 200 mhz, the phas e of pllclk_out2 will have no guar anteed relation to fb_pll_clkin. fabric pll signals table 12 summarizes the key signals of the ql902m fabric pll. table 11: frequency, duty cycle and phase values for fabric pll output pllclk_out2 fabric output pllclk_out2 fd2 fd1 fd0 (f fab ) frequency duty cycle ps1 ps0 phase 0 0 0 f vco 50% x x 0 0 0 1 f vco / 2 50% 0 0 180 0 1 270 1 0 0 1 1 90 010f vco / 3 33% x x 0 0 1 1 f vco / 4 50% 0 0 0 0 1 90 1 0 180 1 1 270 1 x x f vco / 8 50% 0 0 270 0 1 0 1 0 90 1 1 180 table 12: fabric pll i/o signals signal name i/o description fb_pll_clkin i input clock signal. see table 50 for more details. fb_pll_reset_n i active low reset. see table 50 for more details. fb_pll_padout o pll output off chip. see table 50 for more details. pllclk_out o pll output to fabric (1 of 2). this is the pll output clock driven to the fabric clock network. this output runs at the f fab frequency described in table 10 . furthermore, this output is also phase adjustable. the outpu t frequency and phase is determined by the m(1:0), fd(2:0) and ps(3:2) inputs. pllclk_out2 o pll output to fabric (2 of 2). this is the pll output clock driven to the fabric clock network. this output runs at the f fab frequency described in table 11 . furthermore, this output is also phase adjustable. the outpu t frequency and phase is determined by the m(1:0), fd(2:0) and ps(1:0) inputs.
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 29 note: because fb_pll_clkin, fb_pll_reset_n, and fb_pll_padout have appropriate inpad and outpads included, you do not have to add these pads to your design. advanced clock networks the ql902m device has a large number of extremely advanced and highly flexible clock networks. these consist of three basic types of networks; a global network and a dedicated network (for low-skew applications), and an i/o control/hi-drive netw ork (for high-fanout, multi-load applications). global and dedicated low-skew networks the global and dedicated networks are low-skew networks typically used to drive cl ock signals throughout the entire device. in addition, the global network can also be used to globally drive other high-fanout signals with low skew (e.g., flip-flop set or reset signals). both networks ar e segmented, separated on a per-quadrant basis. (unlike the quicklogic eclipse architec ture, the ql902m has only two quadrants.) figure 15 shows a simplified view of the low-skew clock ne twork architecture in the ql902m device. figure 15: low skew clock architecture lock_detect o active high lock detection signal. this signal is output to the fabric and goes high when the pll vco is locked to the input clock reference. m(1:0) i vco frequency multiplier input. these inputs are statically driven high or low by the fabric. see table 9 for their effect on pll operation. fd(2:0) i fabric output frequency divide input. these inputs are statically driven high or low by the fabric. see table 10 for their effect on pll operation. ps(3:2) i phase select input for fabric output. these inputs are statically driven high or low by the fabric. see table 10 for their effect on pll operation. ps(1:0) i phase select input for fabric output2. these inputs are statically driven high or low by the fabric. see table 11 for their effect on pll operation. table 12: fabric pll i/o signals (continued) signal name i/o description global and dedicated networks clk pin upper left upper right
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 30 table 13 shows the number of global and dedicated ne tworks available per qu adrant in the ql902m. as table 13 shows, there are a total of nine low-skew netw orks per quadrant in the ql902m, making a total of eighteen in the entire device. each quadrant cont ains eight global networks and one dedicated network. the global network and dedicated network differ slight ly in performance and fl exibility. the dedicated network offers superb low-skew and minimal pin to lo gic element delay performance, but can only drive the clock inputs of specific fabric elements. the global netw ork offers more flexibility to drive a variety of inputs in the fabric as well as internal assp port in puts, but at a slight increase in skew and delay. table 14 outlines all allowable input destinations for each clock network type. each quadrant consists of an element called the pllmux that drives the global networks and the dedicated network in the quadrant. the pllmux selects between external clk input pins and clock signals that are driven from other elements internal to the device su ch as the fabric pll and the assp system bus clock (hclk). figure 16 shows a simplified schematic diagram of the clk input pins, the pllmux elements and the associated clock networks. table 13: number of ql902m low-skew clock networks clock network type quadrant total upper left upper right global 8 (5 are quad-nets) 8 (5 are quad-nets) 16 dedicated 1 1 2 to t a l 9 9 18 table 14: allowable inputs destinations for global and dedicated networks element inputs that can be driven by the global clock network inputs that can be driven by the dedicated clock network logic cells qc qc a2 f1 qs qr ram modules wclk wclk rclk re rclk we ecus clk - reset i/o cells iqc iqc iqr eqe iqe ie assp interface all inputs -
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 31 figure 16: low skew clock structure schematic based upon pllmux elements (1 of 2 quadrants) logic element x x pllclk_out clk(3) input pin global clock network t pgck t bgck logic element x x no connection global clock network t pgck t bgck logic element x x pllclk_out2 dedicated clock network t pdedclk logic element x x hclk clk(2) input pin global clock network t pgck t bgck pll mux pll mux pll mux pll mux clk(4)/dedclk input pin clk(5) input pin
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 32 if either of the fabric pll outputs or hclk are utilized in a given quadrant of the fabric design, the quickworks software automatically configures the corresponding pllmux to select the internal clock input. each quadrant consists of four pllmux elements of which one inpu t is tied to a specific clk input pin as shown in table 15 . as table 15 indicates, once a pllmux is used to drive an internal signal onto the global or dedicated networks, the corresponding clk input pin is blocked from entering that quadrant. note: if either of the fabric pll outputs or hclk are utiliz ed in the fabric design, and external clock pins are also utilized, the designer should choose clock in put pins on the device that do not conflict with these corresponding pllmux elements. quad-net network (subset of the global network) in each quadrant, the remaining five global networks ar e also referred to as quad-net networks. quad-nets are networks that can be driven by input clk pins or by signals that are generate d internally to the fabric. quad-nets are driven by an element in the fabric called the hsckmux. figure 17 shows a simplified schematic diagram of the clk input pins, the hsckmu x elements and the associated quad-net networks. table 15: pllmux input signals and output type (per quadrant) input output type pin internal signals clk(2) hclk global clock network clk(3) pllclk_out global clock network clk(4)/dedclk pllclk_out2 dedicated clock network clk(5) - global clock network
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 33 figure 17: low skew clock structure schematic based upon hsckmux elements (1 of 2 quadrants) logic element x x any fabric signal clk(6) input pin t pgck t bgck logic element x x any fabric signal t pgck t bgck logic element x x any fabric signal clk(1) input pin t pgck t bgck hsckmux hsckmux hsckmux clk(7) input pin logic element x x any fabric signal t pgck t bgck hsckmux clk(8) input pin logic element x x any fabric signal clk(0) input pin global clock network (quad-net) t pgck t bgck hsckmux global clock network (quad-net) global clock network (quad-net) global clock network (quad-net) global clock network (quad-net)
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 34 by instantiating the gclkbuff_25um macro with a given fabr ic signal as its input, the designer can program an hsckmux to drive this signal on a quad-net (the qu ickworks tool automatica lly chooses which hsckmux to use). each quadrant consists of five hsckmux elements of which one in put is tied to a specific clk input pin as shown in table 16 . as table 16 indicates, once an hsckmux is used to drive an internal signal onto the quad-net network, the corresponding clk input pin is bloc ked from entering that quadrant. note: if the sum of utilized clock input pins from table 16 and the number of instantiated gclkbuff_25um macros is greater than five, the quickworks software may be unable to successfully resolve the conflicts between the clk input pins and the internally generated clock input signals. this is dependant on several factors, but in most cases can be attributed to the size and complexity of the fabric design. i/o control/hi-drive network the i/o control/hi-drive network is us ed primarily to drive high-fanout (typ ically other than clock or reset) signals throughout the device. each bank of i/os ha s two input-only pins entitled ioctrl that can be programmed to drive the iqc (flip-flop clock), iqr (fli p-flop reset), eqe & iqe (flip-flop enables), and ie (output enable) inputs of each i/o cell in that bank. th ese input-only pins also simultaneously serve as high drive inputs to any logic element input located in the ad jacent quadrant. in addition, the i/o control/hi-drive network can be driven by the internal logic by inst antiating the io_buff_25um ma cro. the ql902m has a total of eight ioctrl input pins which are also shared with the io_buff_25um macros (i.e., if a io_buff_25um macro is utilized at a specific lo cation, the corresponding ioctrl input pin is ignored by the device. the performance of this network is presented in table 35 . general routing network ql902m devices are delivered with six types of rout ing resources as follows: short (sometimes called segmented) wires, dual wires, quad wires, express wire s, distributed networks, and default wires. short wires span the length of one logic cell, always in the vertic al direction. dual wires run horizontally and span the length of two logic cells. short and dual wires are pr edominantly used for local connections. default wires supply v cc and gnd (logic ?1? and logic ?0?) to each column of logic cells. quad wires have passive link interconne ct elements every fourth logic cell. as a result, these wires are typically used to implement intermediate length or medium fan-out nets. express lines run the length of the programmable logi c uninterrupted. each of these lines has a higher capacitance than a quad, dual, or short wire, but less capacitance than shorter wires connected to run the length of the device. the resistance will also be lower because the express wires don' t require the use of ?pass? links. express wires provide higher performance for long routes or high fan-out nets. table 16: hsckmux input signals and output type (per quadrant) input output type pin internal signals clk(0) any signal global clock network (quad-net) clk(1) any signal global clock network (quad-net) clk(6) any signal global clock network (quad-net) clk(7) any signal global clock network (quad-net) clk(8) any signal global clock network (quad-net)
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 35 distributed networks are described in advanced clock networks on page 29. these wires span the programmable logic and are driven by ?column clock? buffers. all clock network pi n buffers (both dedicated and global) are hard wired to indivi dual sets of colu mn clock buffers. programmable i/o the ql902m features a variety of distinct i/o pins to ma ximize performance, functionality, and flexibility with bi-directional i/o pins and input-only pins. all input an d i/o pins are 1.8 v, 2.5 v, and 3.3 v tolerant and comply with the specific i/o standa rd selected. for single-ended i/o standards, vccio(a:d) specifies the input tolerance and the output drive. for example, the v ccio(a:d) pins must be tied to a 3.3 v supply to provide 3.3 v compliance. for voltage referenced i/o standards (e.g, sstl), the voltage supplied to the inref(a:d) pins in each bank specif ies the input switch point. the ql902m can also support the lvds and lvpecl i/o standards with the use of external resistors (see table 17 ). as designs become more complex and requirements more stringent, several application-specific i/o standards have emerged for specific applications. i/o standa rds for processors, memori es, and a variety of bus applications have become commonplace and a requirem ent for many systems. in addition, i/o timing has become a greater issue with specific requirements fo r setup, hold, clock to out, and switching times. the ql902m has addressed these new syst em requirements and in cludes a new i/o cell which consists of programmable i/os as well as a new cell structure consisting of three regist ers?input, output, and oe. the bi-directional i/o pin options can be programmed for input, output, or bi-directional operation. as shown in figure 18 , each bi-directional i/o pin is associated with an i/o cell which features an input register, an input buffer, an output register, a three-state output buffe r, an output enable register, and 2 two-to-one output multiplexers. the select lines of the two-to-one multip lexers are static and must be connected to either v cc or gnd. table 17: i/o standards and applications i/o standard reference voltage output voltage application lv t t l n/a 3.3 v general purpose lv c m o s 2 5 n/a 2.5 v general purpose lv c m o s 1 8 n/a 1.8 v general purpose pci n/a 3.3 v pci bus applications gtl+ 1 n/a backplane sstl3 1.5 3.3 v sdram sstl2 1.25 2.5 v sdram
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 36 figure 18: ql902m i/o cell for input functions, i/o pins can prov ide combinatorial, registered data, or both options simultaneously to the logic array. for combinatorial input operation, data is routed from i/o pins through the input buffer to the array logic. for registered input operation, i/o pins driv e the d input of the input registers, allowing data to be captured with fast se t-up times without consuming internal logi c cell resources. the comparator and multiplexor in the input path allows for native support of i/o standards with reference points offset from traditional ground. for output functions, i/o pins can receive combinatorial or registered data from the logic array. for combinatorial output operation, data is routed from th e logic array through a multiplexer to the i/o pin. for registered output operation, the array logic drives the d input of the output register which in turn drives the i/o pin through a multiplexer. the multip lexer allows either a combinatorial or a registered signal to be driven to the i/o pin. using the output register will also decr ease the tco. since the output register does not need to drive the routing the length of th e output path is also reduced. the three-state output buffer controls the flow of data from the array logic to the i/o pin and allows the i/o pin to act as an input and/or output. the buffer's output enable can be indi vidually controlled by the logic cell array or any pin (through the regular routing resources), or it can be bank-controlled through one of the global networks. the signal can also be either combinatorial or re gistered. this is identical to that of the flow for the output register. for combinatorial control operation data is routed from the logic array through a multiplexer to the three-state control. the ioctrl pins can directly drive the oe and clk signals for all i/o cells within the same bank. for registered control operation, the array logic drives th e d input of the oe register which in turn drives the three-state control through a multiplexer. the multiplexer allows either a combinatorial or a registered signal to be driven to the three-state control. when i/o pins are unused, the oe cont rols can be permanently disabled, a llowing the output register to be used for registered feedback into the logic array. e q r d q r d e q r d > > > + - pad input register output register output enable register ip iz iqe iqq osel oqq oqi esel eqe ie iqr iqc
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 37 i/o cell registers are controlled by clock, clock enable , and reset signals, which can come from the regular routing resources, from one of the global networks, or from two ioctrl input pins per bank of i/os. the clk and reset signals share common lines, while the cl ock enables for each regist er can be independently controlled. i/o interface support is programmable on a per bank basis. th e ql902m contains four i/o banks. figure 19 illustrates the i/o bank configurations. each i/o bank is independent of other i/o banks an d each i/o bank has its own vccio and inref supply inputs. a mixture of different i/o standards can be used on the device; however, there is a limitation as to which i/o standards can be supporte d within a given bank. only standa rds that share a common vccio and inref can be shared within the same bank (e.g., pci and lvttl). figure 19: multiple i/o banks programmable slew rate each i/o has programmable slew rate capability?the slew rate can be ei ther fast or slow. the slower rate can be used to reduce the switching noise of each i/o. see table 41 through table 43 for specific information on the slew rates for the fabric i/o pins. the option to chan ge the slew rate is selectable through quickworks in the tools/configure pins window in spde. programmable weak pull-down a programmable weak pull-down resistor is available on each i/o. the i/o weak pull-down eliminates the need for external pull down resistors for used i/os . the spec for pull-down current is maximum of 150 a under worst case conditions. the option to use the programmable weak pull-down resistor is selectable through quickworks in the tools/configure pins window in spde. fabric embedded ram blocks pll embeded computational units embedded ram blocks vccio(c) inref(c) vccio(b) inref(b) vccio(a) inref(a) inref(d) vccio(d) assp ioctrl(d) ioctrl(c) ioctrl(b) ioctrl(a)
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 38 figure 20: programmable i/o weak pull-down global power-on reset (por) the ql902m family of devices features a global power-on re set. this reset is hardwired to all registers and resets them to logic ?0? upon power-up of the device . in quicklogic devices, the asynchronous reset input to flip-flops has priority over the se t input; therefore, the global por will reset all flip-flops during power-up. if you want to set the flip-flops to logic ?1?, you must assert the ?set? signal after the global por signal has been deasserted. this is accomplish ed by holding the ?set? signal high for at least 1 ms after the v cc supply has reached 1.95 v. figure 21: power-on reset i/o output logic pad vcc power-on reset q 0 xxxxxxxxxxxx
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 39 joint test access group (jtag) figure 22: jtag block diagram microprocessors and application specific integrated circuits (asics) pose many design challenges, one problem being the accessibility of test points. jtag fo rmed in response to this ch allenge, resulting in ieee standard 1149.1, the standard test access port and boundary scan architecture. the jtag boundary scan test methodology allows complete observation and control of the boundary pins of a jtag-compatible device through jtag software. a test access port (tap) controller works in concert with the instruction register (ir), which allow users to run th ree required tests along with several user-defined tests. jtag tests allow users to reduce syst em debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. the 1149.1 standard requires the following three tests: extest instruction. the extest instruction performs a pcb inte rconnect test. this te st places a device into an external boundary test mode, selecting the bo undary scan register to be connected between the taps test data in (tdi) and test data out (tdo) pins . boundary scan cells are preloaded with test patterns (through the sample/preload instruction), and input boundary cells capture the input data for analysis. sample/preload instruction. this instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connect ed between the tdi and tdo pins. for this test, the boundary scan register can be accessed through a da ta scan operation, allowing users to sample the functional data entering and leaving the device. tck tms trstb rdi tdo instruction decode & control logic tap controller state machine (16 states) instruction register boundary-scan register (data register) mux bypass register mux internal register i/o registers user defined data register
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 40 bypass instruction. the bypass instruction allows data to skip a device's boundary scan entirely, so the data passes through the bypass regist er. the bypass instruction allows user s to test a device without passing through other devices. the bypass register is conn ected between the tdi and tdo pins, allowing serial data to be transferred through a device wi thout affecting the operation of the device. jtag bsdl support bsdl-boundary scan description language machine-readable data for test equipmen t to generate testing vectors and software bsdl files available for all device /package combinations from quicklogic extensive industry support available and at vg (automatic test vector generation) security links there are several security links: to disable reading lo gic from the array, and to disable jtag access to the device. programming these optional links completely disa bles access to the device from the outside world and provides an extra level of design security not possible in sram-based fpgas. the option to program these links is selectable through quickworks in the t ools/options/device programming window in spde. power-up loading link the flexibility link enables power-up loading of the embedded ram blocks. if the link is programmed, the power up loading state machine is activated during power-up of the device. the state machine communicates with an external eprom via the jtag pins to download memory contents into the on-chip ram. if the link is not programmed, power-up loadin g is not enabled and the jtag pins function as they normally would. the option to program this link is selectable throug h quickworks in the tools/options/device programming window in spde. for more information on power-up loading, see quicklogic application note 55 at http://www.quicklogic.com/images/appnote55.pdf . see the power-up loading power-up sequencing requirement for proper functionality in figure 23 .
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 41 figure 23: required power-up sequence when using power-up loading voltage v ccio v3v v cc time < 2 ms v cc
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 42 electrical specifications dc characteristics the dc specifications are provided in table 18 through table 23 . table 18: absolute maximum ratings parameter value parameter value vcc voltage -0.5 v to 2.0 v latch-up immunity 100 ma vccio(a:d) voltage -0.5 v to 4.0 v dc input current 20 ma inref(a:d) voltage 0.5 v to vccio(a:d) bga package storage temperature -55 c to +125 c input voltage -0.5 v to vccio(a:d) + 0.5 v v3v voltage -0.5 v to 4.0 v table 19: operating range symbol parameter industrial commercial unit min. max. min. max. vcc supply voltage 1.90 2.00 1.90 2.00 v v3v assp i/o supply voltage 3.00 3.60 3.00 3.60 v vccio(a:d) fabric i/o bank supply voltages 1.71 3.60 1.71 3.60 v t j junction temperature -40 100 0 85 c k delay factor -1 speed grade 0.48 1.32 0.51 1.29 n/a -2 speed grade 0.47 1.17 0.50 1.14 n/a
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 43 table 20: dc characteristics symbol parameter conditions min. max. units i cc d.c. supply current v i , v o = v3v, vccio(a:d) or gnd - tbd ma i cc(static) d.c. supply current, static v i , v o = v3v, vccio(a:d) or gnd, all clock inputs are 0 mhz - 600 a i v3v d.c. supply current on v3v v3v = 3.3 v - tbd ma table 21: fabric i/o dc characteristics symbol parameter conditions min. max. units i i i or i/o input leakage current v i = vccio(a:d) or gnd -1 1 a i oz 3-state output leakage current v i = vccio(a:d) or gnd - 1 a c i i/o input capacitance a a. capacitance is sample tested only. - - 8 pf c clock clock input capacitance a - - 12 pf i os output short circuit current b b. only one output at a time. dura tion should not exceed 30 seconds. v o = gnd v o = vccio(a:d) -15 40 -180 210 ma ma i ref d.c. supply current on inref(a:d) - -10 10 a i pd current on programmable pull-down vccio(a:d) = 3.6 v vccio(a:d) = 2.5 v vccio(a:d) = 1.8 v - 150 a i ccio d.c. supply current on vccio(a:d) vccio(a:d) = 3.6 v vccio(a:d) = 2.5 v vccio(a:d) = 1.8 v - 10 10 20 a
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 44 table 22: assp i/o dc characteristics symbol parameter conditions min. typ. max. units i i i or i/o input leakage current v i = v3v or gnd -1 1 a i oz 3-state output leakage current v i = v3v or gnd - tbd a c i i/o input capacitance a a. capacitance is sample tested only. - 7 pf c clock clock input capacitance a - 7 pf i os output short circuit current b b. only one output at a time. duration should not exceed 30 seconds. v o = gnd v o = v3v tbd tbd tbd tbd ma ma v rst_tl cpu_reset_n, cpu_warmreset_n, ejtag_trst_n input low threshold v3v = 3.3 v 0.90 1.24 1.46 v v rst_th cpu_reset_n, cpu_warmreset_n, ejtag_trst_n input high threshold v3v = 3.3 v 1.39 1.82 2.06 v v rst_hys cpu_reset_n, cpu_warmreset_n, ejtag_trst_n input hysteresis v3v = 3.3 v 0.49 0.51 0.54 v table 23: fabric dc input and output levels a a. the data provided in table 23 are jedec and pci specifications. quickl ogic devices either meet or exceed these requirements. note: all clk and ioctrl input pins are clamped to the v3v rail. therefore, these pains can be driven up to v3v+0.3v. inref v il v ih v ol v oh i ol i oh v min v max v min v max v min v max v max v min ma ma lv t t l n/a n/a -0.3 0.8 2.2 vccio(a:d) + 0.3 0.4 2.4 2.0 -2.0 lv c m o s 2 n/a n/a -0.3 0.7 1.7 vccio(a:d) + 0.3 0.7 1.7 2.0 -2.0 lv c m o s 1 8 n/a n/a -0.3 0.63 1.2 vccio(a:d) + 0.3 0.7 1.7 2.0 -2.0 gtl+ 0.88 1.12 -0.3 inref(a:d) - 0.2 inref(a:d) + 0.2 vccio(a:d) + 0.3 0.6 n/a 40 n/a pci n/a n/a -0.3 0.3 x vccio(a:d) 0.5 x vccio(a:d) vccio(a:d) + 0.5 0.1 x vccio(a:d) 0.9 x vccio(a:d) 1.5 -0.5 sstl2 1.15 1.35 -0.3 inref(a:d) - 0.18 inref(a:d) + 0.18 vccio(a:d) + 0.3 0.74 1.76 7.6 -7.6 sstl3 1.3 1.7 -0.3 inref(a:d) - 0.2 inref(a:d) + 0.2 vccio(a:d) + 0.3 1.10 1.90 8 -8
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 45 figure 24 through figure 24 show the vil and vih characteristics for fabric i/o and clock pins. figure 24: vil maximum for fabric i/o figure 25: vih minimum for fabric i/o vilmax for io 0 0.5 1 1.5 2 2.5 -55c -40c 0c 25c 70c 90c 110c 125c junction temperature voltage (v) 1.71 1.8 1.89 2.5 3.3 3.6 vihmin for io 0 0.5 1 1.5 2 2.5 -55c -40c 0c 25c 70c 90c 110c 125c junction temperature voltage 1.71 1.8 1.89 2.5 3.3 3.6
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 46 figure 26: vil maximum for fabric clock pins figure 27: vih minimum for fabric clock pins vilmax for clock pins 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 -55c -40c 0c 25c 70c 90c 110c 125c junction temperature voltage (v) 1.71 1.8 1.89 2.5 3.3 3.6 vihmin for clock pins 0 0.5 1 1.5 2 2.5 -55c -40c 0c 25c 70c 90c 110c 125c junction temperature voltage (v) 1.71 1.8 1.89 2.5 3.3 3.6
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 47 figure 28 through figure 32 show the output drive characteristics for the fabric i/os across various voltages and temperatures. figure 28: drive current at vccio = 1.71 v figure 29: drive current at vccio = 1.8 v drive current @ vccio = 1.71 0 5 10 15 20 25 30 35 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.71 output voltage (v) drive current (ma ) ioh: 55c iol: 55c ioh: 25c iol: 25c ioh: 125 iol: 125 drive current @ vccio = 1.8 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 output voltage (v) drive current (ma) ioh: 55c iol: 55c ioh: 25c iol: 25c ioh: 125 iol: 125
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 48 figure 30: drive current at vccio = 2.5 v figure 31: drive current at vccio = 3.3 v drive current @ vccio = 2.5v 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 output voltage (v) drive current (ma) ioh: 55c iol: 55c ioh: 25c iol: 25c ioh: 125 iol: 125 drive current @ vccio = 3.3v 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.3 output voltage (v) drive current (ma) ioh: 55c iol: 55c ioh: 25c iol: 25c ioh: 125 iol: 125
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 49 figure 32: drive current at vccio = 3.6 v drive current @ vccio = 3.6v 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 2.5 3 3.3 3.6 output voltage (v) drive current (ma) ioh: 55c iol: 55c ioh: 25c iol: 25c ioh: 125 iol: 125
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 50 ac characteristics the ac specifications in this section are shown at v cc = 1.95 v, ta = 25 c, worst case corner, fabric speed grade = -2 (k = 1.01) unless otherwise indicated. assp pll sdram controller figure 33: sdram waveforms table 24: assp pll timing parameters peak to peak jitter vco frequency range minimum lock frequency duty cycle crystal accuracy lock time 200 ps 100 to 300 mhz 80 mhz 45% / 55% 100 ppm 20 s table 25: sdram ac timing symbol parameter a a. all timing is measured with respect to the rising edge of sd_clkin. all measurements are based on i/os with 35 pf load except for sd_clkout, which has a load of 15 pf. ql902m175 ql902m200 units min. max. min. max. t co clock to out, all control and data signals 1.8 7.1 1.6 6.2 ns t su setup time, read data 1.1 - 0.95 - ns t h hold time, read data 0.22 - 0.19 - ns t pd-sdclk maximum allowed delay, sd_clkout to sd_clkin - 2.81 - 2.45 ns sd_clkin addr[23:0] sd_cs_n[3:0] sd_cke[3:0] sd_dqm[3:0] sd_ras_n sd_cas_n sd_we_n data(output)[31:0] data(input[31:0] tco_sdram tsu_sdram th_sdram sd_clkout tpd-sdclk
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 51 i/o peripheral controller figure 34: sram read waveforms figure 35: sram write waveforms table 26: sram ac read timing requirements symbol parameter ql902m175 ql902m200 units min. max. min. max. d0 access time, address and byte lane output to read data valid a a. measurement is based on sd_clkin feedback with 0 ns delay and sd_clkout load of 15 pf. allowed access time will be decreased by sd_clkin to sd_clkout delay. - 8.3 - 7.3 ns d1 access time, output enable to read data valid - 13.9 - 12.1 ns table 27: sram ac write timing characteristics symbol parameter ql902m175 ql902m200 units min. max. min. max. d0 write enable low pulse width 1 - 1 - hclk period d1 write output data valid before rising edge of write enable a a. measurement is based on sd_clkin feedback with 0 ns delay and sd_clkout load of 15 pf. setup time will be decreased by sd_clkin to sd_clkout delay. 4.7 - 4.1 - ns internal_ahb_clock cs_n addr[31:0] bls_n[3:0] oen_n wen_n data[31:0] addr addr byte lane select byte lane select read data read data d0 d1 internal_ahb_clock cs_n addr [31:0] bls_n[3:0] oen_n wen_n data[31:0] addr addr byte lane select byte lane select write data write data d0 d1
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 52 pci controller figure 36: pci waveforms pci_clk pci_ad(output)[31:0] pc i_ c_ be _ n( ou tp u t) [3 : 0] pc i_ p ar (ou tpu t) p ci_fr am e_ n( ou tpu t) pci_irdy_n(output) pci_trdy_n(output) pci_stop_n(output) pci_devsel_n(output) pci_serr_n pci_perr_n(output) pci_req_n pci_ad(input)[31:0] pci_c_be_n(input)[3:0] pci_par(input) pci_frame_n(input) pci_irdy_n(input) pci_trdy_n(input) pci_ st op _ n(i np ut) pci_devsel_n(input) pci_idsel pc i_ p err _n (in pu t) pci_ lock_ n pci_gnt_n tval tsu th tval(ptp) tsu(ptp)
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 53 table 28: pci ac timing parameter a a. all pci pins are synchronous to the pci clock except for pci_rst_n and pci_inta_n. 66 mhz 33 mhz units min. max. min. max. t cyc pci_clk cycle time 15 - 30 - ns t high pci_clk high time 6 - 11 - ns t low pci_clk low time 6 - 11 - ns ? pci_clk slew rate 1.5 4 1 4 v/ns t val pci_clk to signal valid delay 2 6 2 11 ns t val (ptp) pci_clk to signal valid delay point-to-point signals b b. point-to-point signals include pci_req_n and pci_gnt_n. 2 6 2 12 ns t on float to active delay 2 - 2 - ns t off active to float delay - 14 - 28 ns t su input setup time to pci_clk bused signals 3 - 7 - ns t su (ptp) input setup time to pci_clk point-to-point 5 - 10, 12 - ns t h input hold time from pci_clk 0 - 0 - ns t rst reset active time after power stable 1 - 1 - ms t rst-clk reset active time after pci_clk stable 100 - 100 - s t rst-off c c. all output drivers must be 3- stated when pci_rst_n is active. reset active to output float delay 40 40 ns t rhfa pci_rst_n high to first configuration access 2 - 2 - clocks t rhff pci_rst_n high to first pci_frame_n assertion 5 - 5 - clocks
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 54 system sram figure 37: system sram block diagram sram block system target interface 4k sram (1024x32) read data 32 gl_sr_select register fabric sram 1 interface address, write data, clock, and control 4k sram (1024x32) read data 32 sram 2 interface address, write data, clock, and control 4k sram (1024x32) read data sram 3 interface address, write data, clock, and control 4k sram (1024x32) read data sram 4 interface address, write data, clock and control system bus 32 32 48 48 48 48
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 55 figure 38: system sram fabric interface read timing (one sram interface shown) figure 39: system sram fabric interface write timing (one sram interface shown) note: for timing values relate d to each individual assp sram block, refer to table 46 and table 47 . table 29: system sram fabric interface timing symbol parameter ql902m175 ql902m200 units min. max. min. max. t sa setup time, address input 1.40 - 1.23 - ns t ha hold time, address input 0.48 - 0.42 - ns t swd setup time, write data input 1.81 - 1.59 - ns t hwd hold time, write data input 0.56 - 0.49 - ns t swe setup time, write enable input 0.60 - 0.53 - ns t hwe hold time, write enable input 0.54 - 0.48 - ns t sweb setup time, byte write enable input 1.13 - 0.99 - ns t hweb hold time, byte write enable input 0.94 - 0.82 - ns t cord clock-to-out time, read data output - 5.17 - 4.52 ns
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 56 logic cells figure 40: ql902m logic cell figure 41: logic cell flip-flop a1 a2 a3 a4 a5 a6 az oz qz nz q2z fz os op b1 b2 c1 c2 mp ms dq dq d1 d2 e1 e2 np ns f1 f2 f3 f4 f5 f6 ps pp qc qr qs set d clk reset q
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 57 figure 42: logic cell flip-f lop timings?first waveform figure 43: logic cell flip-flop timings?second waveform set reset q clk t cwhi (min) t cwlo (min) t reset t rw t set t sw clk d q t su t hl t co
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 58 dual-port sram modules figure 44: ram module table 30: logic cells symbol parameter value logic cells min. max. t pd combinatorial delay of the longest path: time taken by the combinatorial circuit to output 0.28 ns 0.95 ns t su setup time: time the synchronous input of the flip-flop must be stable before the active clock edge 0.25 ns - t hl hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0 ns - t co clock-to-out delay: the amount of time tak en by the flip-flop to output after the active clock edge. 0.22 ns 0.52 ns t cwhi clock high time: required minimum time the clock stays high 0.46 ns - t cwlo clock low time: required minimum time that the clock stays low 0.46 ns - t set set delay: time between when the flip-fl op is ?set? (high an d when the output is consequently ?set? (high) - 0.69 ns t reset reset delay: time between when the flip-flop is ?reset? (low) and when the output is consequently ?reset? (low) - 1.09 ns t sw set width: time that the set signal must remain high/low 0.3 ns - t rw reset width: time th at the reset signal must remain high/low 0.3 ns - wa wd we wclk re rclk ra rd ram module [7:0] [17:0] [7:0] [17:0] asyncrd
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 59 figure 45: ram cell synchronous write timing table 31: ram cell synchronous write timing symbol parameter value min. max. ram cell synchronous write timing t swa wa setup time to wclk: time the wr ite address must be stable before the active edge of the write clock 0.675 ns - t hwa wa hold time to wclk: time the write address must be stable after the active edge of the write clock 0 ns - t swd wd setup time to wclk: time the write data must be stable before the active edge of the write clock 0.654 ns - t hwd wd hold time to wclk: time the write data must be stable after the active edge of the write clock 0 ns - t swe we setup time to wclk: time the write enable must be stable before the active edge of the write clock 0.623 ns - t hwe we hold time to wclk: time the write enable must be stable after the active edge of the write clock 0 ns - t wcrd wclk to rd (wa = ra): time between the active write clock edge and the time when the data is available at rd - 4.38 ns t swa t swd t swe t hwa t hwd t hwe t wcrd old data new data wclk wa wd we rd
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 60 figure 46: ram cell synchronous and asynchronous read timing table 32: ram cell synchronous and asynchronous read timing symbol parameter value min. max. ram cell synchronous read timing t sra ra setup time to rclk: time the read address must be stable before the active edge of the read clock 0.686 ns - t hra ra hold time to rclk: time the read address must be stable after the active edge of the read clock 0 ns - t sre re setup time to wclk: time the read en able must be stable before the active edge of the read clock 0.243 ns - t hre re hold time to wclk: time the read en able must be stable after the active edge of the read clock 0 ns - t rcrd rclk to rd: time between the active read clock edge and the time when the data is available at rd - 4.38 ns ram cell asynchronous read timing r pdrd ra to rd: time between when the read address is input and when the data is output - 2.06 ns t sra t hra rclk ra t sre t hre t rcrd old data new data re rd r pdrd
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 61 ecus figure 47: ecu block diagram note: timing numbers in table 33 represent -2 worst case commercial conditions. table 33: ecu mode select criteria instruction operation ecu performance a , -2 wcc a. t pd , t su , and t co do not include routing paths in/out of the ecu block. s1 a2 s3 t pd t su t co 0 0 0 multiply 6.6 ns max. - - 0 0 1 multiply-add 8.8 ns max. - - 0 1 0 accumulate b b. internal feedback path in ecu restricts max. clk frequency to 238 mhz. - 3.9 ns min. 1.2 ns max. 0 1 1 add 3.1 ns max. - - 1 0 0 multiply (registered) c c. b (15:0) set to zero. - 9.6 ns min. 1.2 ns max. 1 0 1 multiply-add (registered) - 9.6 ns min. 1.2 ns max. 1 1 0 multiply-accumulate - 9.6 ns min. 1.2 ns max. 1 1 1 add (registered) - 3.9 ns min. 1.2 ns max. s3 s2 s1 d c b a cin a[15:0] clk b[15:0] sign2 sign1 a[15:8] a[7:0] reset 3-4 decoder 8-bit multiplier 16-bit adder q[16:0] dq 00 01 10
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 62 fabric pll figure 48: ql902m fabric pll block diagram table 34: fabric pll timing parameters peak to peak jitter vco frequency range minimum lock frequency duty cycle crystal accuracy lock time propagation delay fb_pll_clkin to fb_pll_padout 200 ps 100 to 300 mhz 80 mhz 45% / 55% 100 ppm 20 s tbd ns lock detect vco phase frequency detector fb_pll_clkin fb_pll_reset_n phase adj. phase adj. : m : fd fb_pll_padout pllclk_out pllclk_out2 fd = 1, 2, 3, 4 or 8 phase = 0, 90, 180, 270 phase = 0, 90, 180, 270 charge pump m = 2, 4 or 8 fd0 fd1 fd2 m0 m1 ps0 ps1 ps2 ps3 lock_detect
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 63 clock network figure 49: dedicated clock structure schematic table 35: i/o control ne twork/local high-drive destination from pad (max.) from array (max.) i/o (far) 1.00 ns 1.14 ns i/o (near) 0.63 ns 0.78 ns skew 0.37 ns 0.36 ns table 36: dedicated clock network performance symbol parameters value min. max. t pdedclk delay from dedicated clock input pin to logic cell flip-flop - 1.69 ns t skewdedclk skew on dedicated clock network - 0.25 ns t ppll_dedclk delay from fabric pll input pin to logic cell flip-flop - 2.20 ns logic element x x pllclk_out2 dedicated clock network t pdedclk pll mux clk(4)/dedclk input pin fabric pll fb_pll_clkin input pin t ppll_dedclk
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 64 figure 50: global clock structure schematic table 37: global clock network performance symbol parameter value min. max. t pgck global clock pin delay to quad net - 1.95 ns t bgck global clock tree delay (quad net to logic cell flip-flop) - 0.28 ns t skewgck skew on global clock network - 0.25 ns t ppll_gck global clock tree delay, fabric pll input to logic cell flip-flop - tbd ns logic element x x internal signal clk input pin global clock network t pgck t bgck fabric pll x x x x hclk t ppll_gck fb_pll_clkin input pin
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 65 i/o cells figure 51: ql902m input register cell table 38: standard input delays symbol parameter value standard input delays to get the total input delay add this delay to t isu a a. see table 39 for t isu value. min. max. t sid (lvttl) lvttl input delay: low voltage ttl for 3.3 v applications - 0.82 ns t sid (lvcmos2) lvcmos2 input delay: low voltage cmos for 2.5 v and lower applications - 0.82 ns t sid (lvcmos18) lvcmos18 input delay: low voltage cmos for 1.8 v applications - tbd ns t sid (gtl+) gtl+ input delay: gunning transceiver logic - 0.94 ns t sid (sstl3) sstl3 input delay: stub series terminated logic for 3.3 v - 0.94 ns t sid (sstl2) sstl2 input delay: stub series terminated logic for 2.5 v - 0.94 ns t sid (pci) pci input delay: peripheral component interconnect for 3.3 v - 0.82 ns pad t isu t sid + - q e d r
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 66 figure 52: ql902m input register cell timing table 39: input register cell symbol parameter value min. max. input register cell only t isu input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge. 2.15 ns - t ihl input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge. 0 ns - t ico input register clock-to-out: time taken by the flip-flop to output after the active clock edge. - 0.30 ns t irst input register reset delay: time between when the flip-flop is ?reset?(low) and when the output is consequently ?reset? (low). - 0.82 ns t iesu input register clock enable setup time: time ?enable? must be stable before the active clock edge. 0.40 ns - t ieh input register clock enable hold time: time ?enable? must be stable after the active clock edge. 0 ns - r clk d q tisu tih l tic o tiesu tieh tirst e
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 67 figure 53: ql902m output register cell pad output register
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 68 figure 54: ql902m output register cell timing table 40: output register cell symbol parameter value min. max. output register cell only t outlh output delay low to high (90% of h) - 4.46 ns (fast slew) 6.12 ns (slow slew) t outhl output delay high to low (10% of l) - 3.31 ns (fast slew) 5.50 ns (slow slew) t pzh output delay tri-state to high (90% of h) - 4.19 ns (fast slew) 6.22 ns (slow slew) t pzl output delay tri-state to low (10% of l) - 4.19 ns (fast slew) 4.35 ns (slow slew) t phz output delay high to tri-state - 5.97 ns (fast slew) 3.79 ns (slow slew) t plz output delay low to tri-state - 3.58 ns (fast slew) 5.75 ns (slow slew) t cop clock-to-out delay: time taken by the flip-flop to output after the active clock edge. - 6.50 ns (fast slew) tbd ns (slow slew) t outsu output register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge. tbd - t outh output register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge. tbd - t outrst output register reset delay: time between when the flip-flop is ?reset?(low) and when the output is consequently ?reset? (low). - tbd t oesu output enable register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge. tbd - t oeh output enable register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge. tbd - t oerst output enable register reset delay: time between when the flip-flop is ?reset?(low) and when the output is consequently ?reset? (low). - tbd l h l h t outlh t outhl l h z t pzh l h z t pzl l h z t plz l h z t phz
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 69 t oeesu output enable register clock enable setup time: time ?enable? must be stable before the active clock edge. tbd - t oeeh output enable register clock enable hold time: time ?enable? must be stable after the active clock edge. tbd - t oecop output enable register clock-to-out delay: time taken by the flip-flop to output after the active clock edge. - tbd table 40: output register cell (continued) symbol parameter value min. max.
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 70 table 41: fabric output slew rates @ vccio(a:d) = 3.3 v, 25 c fast slew slow slew rising edge 2.8 v/ns 1.0 v/ns falling edge 2.86 v/ns 1.0 v/ns table 42: fabric output slew rates @ vccio(a:d) = 2.5 v, 25 c fast slew slow slew rising edge 1.7 v/ns 0.6 v/ns falling edge 1.9 v/ns 0.6 v/ns table 43: fabric output slew rates @ vccio(a:d) = 1.8 v, 25 c fast slew slow slew rising edge tbd v/ns tbd v/ns falling edge tbd v/ns tbd v/ns table 44: assp output slew rates @ v3v = 3.3 v, 25 c by signal groups assp output group a a. loads are as follows: sdram signals - 35 pf, sd_clkout = 15 pf, sram signals = 50 pf, pci signals = 10 pf, and uart signals = 50 pf. slew (v/ns) maximum slew (v/ns) minimum rising falling rising falling sdram signals (except sd_clkout) 3.00 3.87 0.96 1.12 sd_clkout 4.20 5.30 1.50 1.95 sram control signals 2.30 2/97 0.55 0.58 pci signals 5.35 3.20 1.90 2.43 uart signals 1.33 1.59 0.30 0.30
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 71 assp to fabric timing table 45 through table 47 list the synchronous and asynchronous timing for the ql902m assp to fabric interface ports and assp i/o pins. note th e following regarding the fabric timing: fb_int is asynchronous and is synchronized inside the core. fb_bigendian is a static signal and re flects the value on the cpu_bigendian pin. pm_* and si_* signals are synchronous to the internal mi ps clock which is at least twice the hclk frequency. this internal clock is not driven to the fabric. all af_pci_* signals are static.
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 72 assp to fabric synchr onous output timing table 45: assp to fabric interf ace synchronous output timing clock reference signal ql902m175 t co (ns max.) ql902m200 t co (ns max.) hclk ahb_hready_in 6.05 5.29 hclk ahbm_hgrant 7.63 6.68 hclk ahbm_hrdata(31:0) 7.94 6.95 hclk ahbm_hresp(1:0) 6.05 5.30 hclk ahbs_haddr(31:0) 6.03 5.27 hclk ahbs_hburst(2:0) 5.61 4.90 hclk ahbs_hprot(3:0) 4.75 4.15 hclk ahbs_hsel 6.23 5.45 hclk ahbs_hsize(2:0) 5.63 4.93 hclk ahbs_htrans(1:0) 6.23 5.45 hclk ahbs_hwdata(31:0) 5.92 5.18 hclk ahbs_hwrite 5.55 4.85 hclk apbs_paddr(15:2) 3.06 2.68 hclk apbs_penable 2.98 2.61 hclk apbs_psel0 3.32 2.91 hclk apbs_psel1 3.36 2.94 hclk apbs_psel2 3.31 2.90 hclk apbs_pwdata(31:0) 3.32 2.91 hclk apbs_pwrite 3.05 2.67 hclk hresetn 4.07 3.56 hclk m1_mdc 2.88 2.52 hclk m1_mdo 2.84 2.48 hclk m1_mdo_en_n 2.87 2.51 hclk m2_mdc 3.24 2.84 hclk m2_mdo 3.26 2.85 hclk m2_mdo_en_n 3.30 2.89 cpu_pll_clkout pm_dcachehit 2.99 2.61 cpu_pll_clkout pm_dcachemiss 2.85 2.50 cpu_pll_clkout pm_dtlbhit 2.76 2.42 cpu_pll_clkout pm_dtlbmiss 2.84 2.49 cpu_pll_clkout pm_icachehit 2.86 2.50 cpu_pll_clkout pm_icachemiss 2.70 2.36 cpu_pll_clkout pm_instncomplete 2.60 2.27 cpu_pll_clkout pm_itlbhit 2.72 2.38
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 73 cpu_pll_clkout pm_itlbmiss 2.70 2.36 cpu_pll_clkout pm_jtlbhit 2.61 2.28 cpu_pll_clkout pm_jtlbmiss 2.69 2.35 cpu_pll_clkout pm_wtbmerge 4.49 3.93 cpu_pll_clkout pm_wtbnomerge 2.88 2.52 cpu_pll_clkout si_rp 3.24 2.83 cpu_pll_clkout si_sleep 2.27 1.99 hclk tm_overflow2 2.94 2.57 hclk tm_overflow3 2.85 2.50 hclk tm_overflow4 2.94 2.57 sr1_clk sr1_rdata(31:0) 4.49 3.93 sr2_clk sr2_rdata(31:0) 5.17 4.52 sr3_clk sr3_rdata(31:0) 4.30 3.76 sr4_clk sr4_rdata(31:0) 4.04 3.53 table 45: assp to fabric interface sync hronous output timing (continued) clock reference signal ql902m175 t co (ns max.) ql902m200 t co (ns max.)
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 74 fabric to assp interf ace timing requirements table 46: fabric to assp interface timing requirements clock reference signal ql902m175 ql902m200 t su (ns min) t h (ns min) t su (ns min) t h (ns min) hclk ahbm_haddr(31:0) 3.64 1.39 3.18 1.21 hclk ahbm_hburst(2:0) 3.33 0.03 2.91 0.03 hclk ahbm_hbusreq 3.47 0 3.04 0 hclk ahbm_hprot(3:0) 4.42 0 3.87 0 hclk ahbm_hsize(2:0) 3.07 0.96 2.69 0.84 hclk ahbm_htrans(1:0) 3.56 0.30 3.12 0.26 hclk ahbm_hwdata(31:0) 3.06 1.23 2.68 1.07 hclk ahbm_hwrite 2.98 0.86 2.61 0.75 hclk ahbs_hrdata(31:0) 3.25 0.89 2.84 0.78 hclk ahbs_hready_out 4.15 0.46 3.63 0.40 hclk ahbs_hresp(1:0) 4.03 0.77 3.52 0.67 hclk apbs_prdata0(31:0) 3.44 0.53 3.01 0.46 hclk apbs_prdata1(31:0) 3.42 0.51 3.00 0.45 hclk apbs_prdata2(31:0) 3.34 0.65 2.92 0.57 - m1_col asynchronous input ? no requirement - m1_crs asynchronous input ? no requirement hclk m1_mdi 0 1.38 0 1.20 m1_rxclk m1_rxd(3:0) 0.67 0 0.58 0 m1_rxclk m1_rxdv 1.06 0 0.92 0 m1_rxclk m1_rxer 0.57 0 0.50 0 - m2_col asynchronous input ? no requirement - m2_crs asynchronous input ? no requirement hclk m2_mdi 0 1.62 0 1.42 m2_rxclk m2_rxd(3:0) 0.93 0.35 0.81 0.31 m2_rxclk m2_rxdv 1.65 0 1.45 0 m2_rxclk m2_rxer 0.71 0.09 0.62 0.08 sr1_clk sr1_addr(11:2) 1.18 0.45 1.03 0.39 sr1_clk sr1_wdata(31:0) 1.36 0.15 1.19 0.13 sr1_clk sr1_wen 0.54 0 0.47 0 sr1_clk sr1_wenb(3:0) 0.27 0.66 0.24 0.58 sr2_clk sr2_addr(11:2) 0.93 0.48 0.81 0.42 sr2_clk sr2_wdata(31:0) 1.81 0.48 1.59 0.42 sr2_clk sr2_wen 0.53 0.54 0.46 0.48 sr2_clk sr2_wenb(3:0) 0.43 0.94 0.38 0.82
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 75 sr3_clk sr3_addr(11:2) 0.53 0.34 0.46 0.30 sr3_clk sr3_wdata(31:0) 1.45 0.56 1.27 0.49 sr3_clk sr3_wen 0.21 0.26 0.19 0.23 sr3_clk sr3_wenb(3:0) 0.26 0.59 0.23 0.52 sr4_clk sr4_addr(11:2) 1.40 0.23 1.23 0.20 sr4_clk sr4_wdata(31:0) 1.78 0.15 1.56 0.13 sr4_clk sr4_wen 0.60 0.15 0.53 0.13 sr4_clk sr4_wenb(3:0) 1.13 0.52 0.99 0.46 hclk tm_extclk1 0 1.58 0 1.38 hclk tm_extclk2 0 1.57 0 1.37 hclk tm_extclk3 0 1.57 0 1.37 hclk tm_extclk4 0 1.61 0 1.41 hclk tm_fbenable 0 1.60 0 1.40 table 46: fabric to assp interface timing requirements (continued) clock reference signal ql902m175 ql902m200 t su (ns min) t h (ns min) t su (ns min) t h (ns min)
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 76 assp propagation delays table 47: assp propagation delays starting signal ending signal ql902m175 t pd (ns max) ql902m200 t pd (ns max) path: fabric to fabric through assp ahbm_haddr(31:0) ahbs_haddr(31:0) 1.80 1.57 ahbm_haddr(31:0) ahbs_hsel 2.12 1.86 ahbm_hburst(2:0) ahbm_hgrant 1.78 1.55 ahbm_hburst(2:0) ahbs_hburst(2:0) 2.33 2.04 ahbm_hbusreq ahbm_hgrant 2.66 2.32 ahbm_hprot(3:0) ahbs_hprot(3:0) 1.30 1.14 ahbm_hsize(2:0) ahbs_hsize(2:0) 1.64 1.43 ahbm_htrans(1:0) ahbs_htrans(1:0) 1.86 1.63 ahbm_htrans(1:0) ahbm_hgrant 2.31 2.02 ahbm_hwdata(31:0) ahbs_hwdata(31:0) 1.80 1.57 ahbm_hwrite ahbs_hwrite 1.71 1.49 ahbs_hrdata(31:0) ahbm_hrdata(31:0) 2.37 2.07 ahbs_hready_out ahb_hready_in 1.79 1.57 ahbs_hready_out ahbm_hgrant 3.31 2.90 ahbs_hresp(1:0) ahbm_hgrant 2.07 1.81 ahbs_hresp(1:0) ahbm_hresp(1:0) 3.17 2.77 apbs_prdata0(31:0) ahbm_hrdata(31:0) 2.75 2.41 apbs_prdata1(31:0) ahbm_hrdata(31:0) 2.66 2.33 apbs_prdata2(31:0) ahbm_hrdata(31:0) 2.57 2.25 path: assp input pin to fabric cpu_bigendian fb_bigendian 1.97 1.72 m1_txclk m1_txd(3:0) 2.32 2.03 m1_txclk m1_txen 2.62 2.29 m2_txclk m2_txd(3:0) 3.19 2.79 m2_txclk m2_txen 3.14 2.75 cpu_pll_clkin hclk 1.64 1.43 path: assp input pin to assp output pin cpu_pll_clkin cpu_pll_clkout 2.38 2.09
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 77 package thermal characteristics thermal resistance equations: jc = (t j - t c )/p ja = (t j - t a )/p p max = (t jmax - t amax )/ ja parameter description: jc : junction-to-case thermal resistance ja : junction-to-ambient thermal resistance t j : junction temperature t c : case temperature t a : ambient temperature p: power dissipated by the device while operating p max : the maximum power dissipation for the device t jmax : maximum junction temperature t amax : maximum ambient temperature note: maximum junction temperature (t jmax ) is 125c. to calculate the maximum power dissipation for a device package look up ja from table 48 , pick an appropriate t amax and use: p max = (125oc - t amax )/ ja table 48: package thermal characteristics package description ja (o c/w) @ various flow rates (m/sec) jc (o c/w) pin count package type 0 1 2 2.5 544 pbga 20 16.4 15.5 14.4 8.0
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 78 power vs. operating frequency the basic power equation which best mo dels power consumption is given below: p total (mw) = 0.350 + f fabric [0.0031 lc + 0.0948 ckbf + 0.01 clbf + 0.0263 ckld + 0.543 ram + 0.20 pll + 0.0035 inp + 0.0257 outp ] + 28.1 f asspio + 5.55 f mips where lc = number of logic cells in the design ckbf = number of clock buffers clbf = number of column clock buffers ckld = number of loads connected to the column clock buffers ram = number of ram blocks pll = number of plls inp = number of input pins outp = number of output pins f fabric = average switching frequency of fabric f asspio = average switching frequency of assp i/o signals f mips = cpu operational frequency note: to learn more about power consumption, please refer to application note 60 at http://www.quicklogic.com /images/appnote60.pdf. power-up sequencing figure 55: power-up sequencing when powering up a device, the v cc, vccio and v3v rails must take 400 s or longer to reach the maximum value (refer to figure 55 ). note: ramping vcc, vccio and v3v to the maximum voltage faster than 400 s can cause the device to behave improperly. for users with a limited powe r budget, keep (v3v - vcc) max and (vccio -vcc) max 500 mv when ramping up the power supply. voltage v ccio v3v v cc |v ccio - v cc | max time 400 us v cc |v3v - v cc | max
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 79 board layout recommendations this section describes various recommendations for design and layout of the printed circuit board (pcb) that is used with the ql902m. pll power supply filtering the pll analog powe r supply inputs of the ql902m are: fabric pll: gnd_fb _pll and v3v_fb_pll cpu pll: gnd_cpu_pll and v3v_cpu_pll these signals must be filtered as shown in figure 56 : figure 56: pll power supply filtering circuits for best performance and noise immunity, separate or split power planes for digital ground (gnd), analog ground (fb_pll_gnd and cpu_pll_gnd), digital v cc ( vcc), digital 3.3 v (v3v) and analog 3.3 v (fb_pll_v3v and cpu_pll_ v3v) should be used. v3v_fb_pll gnd_fb_pll v3v_cpu_pll gnd_cpu_pll p22 t21 p5 u6 +3.3 v gnd c 0.1 f c 0.01 f c 0.1 f l r 0 +3.3 v gnd c 0.1 f c 0.01 f c 0.1 f l r 0 0
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 80 bypass capacito r guidelines this section outlines the recommendat ions for capacitive bypassing for the various digital supplies of the ql902m. table 49 indicates the minimum recommended number of 0.1 f and 0.01 f capacitors for each digital supply input on the ql902m. a minimum total quantity of 48 bypass capacitors is recommended. note: all capacitors should be x7r type (or bette r) and 0603 package size is recommended. capacitor placement eight capacitors (all for the v cc supply) should be placed directly un der the device (in the area between the 8x8 gnd pads in the center of the device and the outer rows of signal pads) on the back side of the pcb. the remaining forty capacitors (for the remainder of v cc and all other supplies) shou ld be placed around the perimeter of the chip, also preferab ly on the back side of the board. listed below is the proximity location priority (1=highest ). higher priority filters and/or capacitors should be placed closest to the ql902m. 1. pll bypass capacitors and filter circuitry 2. v cc bypass capacitors 3. vccio/v3v bypass capacitors table 49: minimum recommended number of bypass capacitors for each digital supply input supply input recommended number of capacitors 0.1 f, x7r type (or better) recommended number of capacitors 0.01 f, x7r type (or better) totals vcc 8 8 16 vccio(a) 2 2 4 vccio(b) 2 2 4 vccio(c) 2 2 4 vccio(d) 2 2 4 v3v 8 8 16 to t a l s : 24 24 48
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 81 signal descriptions pin descriptions table 50: pin descriptions pin i/o function pci signals pci_ad(31:0) i/o pci address and data. pci_ad(31:0) contain the multiplexed address and data. a bus transaction consists of a single address phase (or two address phases for 64-bit addresses) followed by one or more data ph ases. the quickmips chip supports both read and write bursts. the address phase occurs in the first cl ock cycle when pci_frame_n is asserted. during the address phase, pci_ ad(31:0) contain a 32-bit physical address. for i/o, this is a byte address; for configuration and memo ry, it is a dword (32-bit) address. during data phases, pci_ad(7:0) contain the least-significant byte, and pci_ad(31:24) contain the most-significant byte. write data is stable and valid when pci_irdy_n is asserted; read data is stable and valid when pci_trdy_n is asserted. data is transferred when both pci_irdy_n and pci_trdy_n are asserted. connect to gnd if the pci controller is unused. pci_c_be_n(3:0) i/o bus command and byte enables. bus commands and byte enables are multiplexed on pci_c_be_n(3:0). during the address phas e of a transaction (pci_frame_n is asserted), pci_c_be_n(3:0) define the bus command as shown in the following table (only valid combinations are shown). pci_c_be_n(3:0) bus command 0000 interrupt acknowledge 0001 special cycle 0010 i/o read 0011 i/o write 0110 memory read 0111 memory write 1010 configuration read 1011 configuration write 1100 memory read multiple 1101 dual address cycle 1110 memory read line 1111 memory write and invalidate during each data phase, pci_c_be_n(3:0) are byte enables. the byte enables are valid for the entire data phase and determine which byte lanes contain meaningful data. pci_c_be_n(0) applies to byte 0 (pci_ad(7:0)) and pci_c_be_n(3) applies to byte 3 (pci_ad(31:24)). connect to gnd if the pci controller is unused. pci_devsel_n i/o pci device select. when asserted low, pci_devsel_n indicates the driving device has decoded its address as the target of the current access. as an input, pci_devsel_n indicates whether any device on the bus has responded. connect to 3.3 v if the pci controller is unused.
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 82 pci_frame_n i/o pci cycle frame. the current master asserts pci_frame_n to indicate the beginning and duration of a bus transaction. whil e pci_frame_n is asserted, data transfers continue. when pci_frame_n is deasserted, the transaction is in the final data phase or has completed. connect to 3.3 v if the pci controller is unused. pci_gnt_n i pci grant. a low assertion of pci_gnt_n indicates to the agent that access to the bus has been granted. pci_gnt_n is ignored while pci_rst_n is asserted. connect to 3.3 v if the pci controller is unused. pci_idsel i pci initialization device select. pci_idsel is used as a chip select during configuration read and write transactions (pci_c_be_n(3:0) = 1010 or 1011). connect to gnd if the pci controller is unused. pci_inta_n o pci interrupt acknowledge. pci_inta_n is a level-sensitive interrupt driven by the quickmips chip. pci_inta_n is asserted and deasserted asynchronously to the pci_clk. this interrupt remains asserted until the interrupt is cleared. because the pci interrupt controller is not built into t he quickmips esp core, this pin is output only. however, such an interrupt controller can be built into the fabric. leave unconnected if the pci controller is unused. pci_irdy_n i/o pci initiator ready. pci_irdy_n is used in conjunction with pci_trdy_n. the bus master (initiator) asserts pci_irdy_n to indicate when there is valid data on pci_ad(31:0) during a write, or that it is ready to accept data on pci_ad(31:0) during a read. a data phase is completed when both pci_irdy_n and pci_trdy_n are asserted. during a write, a low assertion of pci_irdy _n indicates that va lid data is present on pci_ad(31:0). during a read, a low assertion of pci_irdy_n indicates the master is prepared to accept data. wait cycles are inserted until both pci_irdy_n and pci_trdy_n are asserted together. connect to 3.3 v if the pci controller is unused. pci_par i/o pci parity. parity is driven high or low to create even parity across pci_ad(31:0) and pci_c_be_n(3:0). the master drives pci_pa r for address and write data phases; the target drives pci_par for read data phases. connect to 3.3 v if the pci controller is unused. pci_perr_n i/o pci parity error. pci_perr_n indicates the occurrence of a data parity error during all pci transactions except a special cycle. the quickmips chip drives pci_perr_n low two clocks following the data when a data parity error is detected. the minimum duration of the deassertion of pci_perr_n is one cloc k for each data phase that a data parity error is detected. (if sequential data phases each have a data parity error, the pci_perr_n signal is asserted for more than a single clock.) pci_perr_n is driven high for one clock before being 3-stated as with all sustained 3-state signals. connect to 3.3 v if the pci controller is unused. table 50: pin descriptions (continued) pin i/o function
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 83 pci_req_n o pci request. assertion of pci_req_n indicates to the arbiter that this agent desires use of the bus. pci_req_n is 3-st ated while pci_rst_n is asserted. leave unconnected if the pci controller is unused. pci_rst_n i pci reset. asserting pci_rst_n low resets the internal state of the quickmips pci block. when pci_rst_n is asserted, all pci output signals are asynchronously 3-stated. pci_req_n and pci_gnt_n must bot h be 3-stated (they cannot be driven low or high during reset). the assertion/deassertion of pci_rst_n can be asynchronous to pci_clk. connect to gnd if the pci controller is unused. pci_serr_n o pci system error. the quickmips chip asserts pci_serr_n to indicate an address parity error, a data parity error on the specia l cycle command, or any other system error where the result is catastrophic. pci_serr_n is open drain and is actively driven for a single pci clock. the assertion of pci_serr_n is synchronous to the clock and meets the setup and hold times of all bused signals. however, the restoring of pci_serr_n to the deasserted state is accomplished by a weak pull-up (same value as used for s/t/s), which is provided by the central resource not by the signaling agent. this pull-up can take two to three clock periods to fully restore pci_serr_n. leave unconnected if the pci controller is unused. pci_stop_n i/o pci stop. pci_stop_n is asserted low to indicate the current target is requesting the master to stop the current transaction. connect to 3.3 v if the pci controller is unused. pci_trdy_n i/o pci target ready. pci_trdy_n is used in conjunction with pci_irdy_n. the current bus slave (target) asserts pci_trdy_n to indicate when there is valid data on pci_ad(31:0) during a read, or that it is re ady to accept data on pci_ad(31:0) during a write. a data phase is completed when both pci_trdy_n and pci_irdy_n are asserted. during a read, a low assertion of pci_trdy_n indicates that valid data is present on pci_ad(31:0). during a write, a low assertion indicates the target is prepared to accept data. wait cycles are inserted until both pci_irdy_n and pci_trdy_n are asserted together. connect to 3.3 v if the pci controller is unused. pci_clk i pci clock. all pci signals (except pci_rst_n and pci_inta_n) are sampled on the rising edge of pci_clk. pci_clk operates at speeds up to either 33 mhz or 66 mhz. connect to gnd if the pci controller is unused. ethernet mac signals m1_rxclk, m2_rxclk i ethernet receive clock. rxclk is a continuous cloc k that provides the timing reference for the transfer of the rxdv a nd rxd(3:0) signals from the ethernet phy controller to the mac core. the ethernet ph y controller chip sources rxclk. rxclk has a frequency equal to 25% of the data rate of the received signal on the ethernet cable. connect to gnd if the ethernet controller is unused. table 50: pin descriptions (continued) pin i/o function
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 84 m1_txclk, m2_txclk i ethernet transmit clock. txclk is a continuous clock that provides a timing reference for the transfer of the txen and txd signal s from the mac core to the ethernet phy controller. the ethernet phy controller chip sources txclk. the operating frequency of txclk is 25 mhz when operating at 100 mbps and 2.5 mhz when operating at 10 mbps. connect to gnd if the ethernet controller is unused. memory controller interface signals bls_n(3:0) o sram byte enables. bls_n(3:0) indicates the validity of the bytes on data(31:0) for external sram read and write accesses. bls_n(3) corresponds to data(31:24) bls_n(2) corresponds to data(23:16) bls_n(1) corresponds to data(15:8) bls_n(0) corresponds to data(7:0) cs_n(7:0) o chip selects. these signals are the active-low chip selects for the sram. addr(23:0) o memory address. this 24-bit bus contains the memory address for external sram and sdram accesses. data(31:0) i/o memory data. this 32-bit bus contains the memory read/write data for sram and sdram accesses. oe_n o sram output enable. oe_n is the active-low output enable to the external sram. sd_cas_n o sdram column address strobe. sd_cas_n is the active-low column address strobe for the external sdram. sd_cke(1:0) o sdram clock enables. if low, these signals indicate to the externally connected sdram to enter the power-down state. sd_clkin i sdram input clock. sd_clkin should be tied to sd_clkout on the pcb. internal to the quickmips device, all sdram command, address and data signals are synchronized with sd_clkin. if a clock buffer is used to drive the sdram devices, this buffer should be a zero-delay type buffer, and sd_clkin should be tied to one of the buffer outputs. sd_clkout o sdram output clock. sd_clkout is the clock source for the externally connected sdrams. this signal may be connected to a zero-delay buffer to drive multiple sdram devices. sd_clkout is equal in frequency to the internal system bus clock and hclk. see table 2 for additional details. sd_cs_n(1:0) o sdram output chip select. sd_cs_n(1:0) are the active-low chip selects for the external sdrams. sd_dqm(3:0) o sdram data mask. sd_dqm(3:0) are the data masks for data(31:0) during sdram read and write accesses. sd_dqm(3) correspond s to data(31:24) sd_dqm(2) correspond s to data(23:16) sd_dqm(1) corresponds to data(15:8) sd_dqm(0) corresponds to data(7:0) sd_ras_n o sdram row address strobe. sd_ras_n is the active-low row address strobe for the external sdram. sd_we_n o sdram write enable. sd_we_n is the active-low write enable to the sdrams. we_n o sram write enable. we_n indicates whether transactions between the quickmips chip and the external sram are reads (we_n is high) or writes (we_n is low). table 50: pin descriptions (continued) pin i/o function
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 85 uart interface signals u1_cts_n i uart1 clear to send. a low on this signal indicates the external device is ready to transfer data. connect to gnd if the uart is unused. u1_dcd_n i uart1 data carrier detect. a low on this signal indicates the data carrier has been detected. connect to gnd if the uart is unused. u1_dsr_n i uart1 data set ready. a low on this signal indicates the modem or data set is ready to establish the link to the quickmips uart. connect to gnd if the uart is unused. u1_dtr_n o uart1 data terminal ready. the quickmips chip asserts this output low to indicate it is ready to establish the external communication link. leave unconnected if the uart is unused. u1_ri_n i uart1 ring indicator. this input is an active-low ring indicator. connect to 3.3 v if the uart is unused. u1_rts_n o uart1 request to send. the quickmips chip asserts this signal low to inform the external device that the uart is ready to send data. leave unconnected if the uart is unused. u1_rxd_sirin i uart1 receive serial data/s ir receive serial data. this input receives serial data from either the uart or the irda block. connect to gnd if the uart is unused. u1_txd_sirout o uart1 transmit serial data/sir transmit serial data. this output transmits serial data to either the uart or irda block. leave unconnected if the uart is unused. u2_rxd_sirin i uart2 receive serial data/sir receive serial data. this input receives serial data from either the uart or the irda block. connect to gnd if the uart is unused. u2_txd_sirout o uart2 transmit serial data/sir transmit serial data. this output transmits serial data to either the uart or irda block. leave unconnected if the uart is unused. test interface signals ejtag_tck i ejtag test clock. this clock controls the updates to the tap controller and the shifts through the instruction register or selected data registers. both the rising and falling edges of ejtag_tck are used. connect to 3.3 v through a 1 k resistor. ejtag_tdi i ejtag test data in. serial test data is input on this pi n and is shifted into the instruction or data register. this input is sampled on the rising edge of ejtag_tck. connect to 3.3 v through a 1 k resistor. table 50: pin descriptions (continued) pin i/o function ? ?
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 86 ejtag_tdo o ejtag test data out. the quickmips chip outputs serial test data on this pin from the instruction or data register. this signal changes on the falling edge of ejtag_tck. connect to 3.3 v through a 10 k resistor. ejtag_tms i ejtag test mode select. this input is the control signal for the tap controller. it is sampled on the rising edge of ejtag_tck. connect to 3.3 v through a 1 k resistor. ejtag_trst_n i ejtag test reset. this signal is asserted asynchronously to reset the tap controller, instruction register, and ejtagboot indication. connect to gnd through a 1 k resistor. ejtag_debugm o debug mode. this bit is asserted high when the mips 4kc core is in debug mode. this output can be used to bring the chip out of low power mode. ejtag_dint i debug exception request. assertion high of this input indicates a debug exception request is pending. the request is cleared w hen debug mode is entered. requests that occur while the chip is in debug mode are ignored. connect to 3.3 v through a 1 k resistor. fabric interface signals i/o(a) i/o programmable input/output/3-state /bidirectional pin in bank a. if an i/o is not used, spde (quick works tool) provides the option of tying that pin to gnd, v cc, or tristate during programming. i/o(b) i/o programmable input/output/3-state/bidirectional pin in bank b. if an i/o is not used, spde (quick works tool) provides the option of tying that pin to gnd, v cc, or tristate during programming. i/o(c) i/o programmable input/output/3-state /bidirectional pin in bank c. if an i/o is not used, spde (quick works tool) provides the option of tying that pin to gnd, v cc, or tristate during programming. i/o(d) i/o programmable input/output/3-sta te/bidirectional pin in bank d. if an i/o is not used, spde (quick works tool) provides the option of tying that pin to gnd, v cc, or tristate during programming. clk(8:5) clk(3:0) i programmable global clock pin. this pin provides access to a dedicated, distributed network capable of driving the clock, set, reset, f1, and a2 inputs to the logic cell, read, and write clocks, read and write enables of the embedded ram blocks, clock of the ecus, and output enables of the i/os. connect to 3.3v or gnd if unused. clk(4)/ dedclk i low skew dedicated clock. this pin provides access to a dedicated, distributed clock network capable of driving the clock inputs of all sequential elements of the device (e.g., ram, flip-flops). connect to 3.3v or gnd if unused. inref(a:d) i differential i/o reference voltage. inref is the reference voltage pin for gtl+, sstl2, and sttl3 standards. follow the recommendations provided in table 23 for the appropriate standard. connect to gnd when using ttl, pci or lvcmos. table 50: pin descriptions (continued) pin i/o function ? ? ? ?
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 87 ioctrl(a:d) i high drive i/o control pins. this pin provides fast reset, set, clock, and enable access to the i/o cell flip-flops, providing fast clock-to-out and fast i/o response times. this pin can also double as a high-drive pin to the internal logic cells. there is an internal pull-down resistor to gnd on this pin. this pin should be tied to gnd if it is not used. if tied to 3.3 v, it will draw no more than 20 a per ioctrl pin due to the pull-down resistor. fabric jtag signals tdi/rsi i test data in for jtag/ram init. serial data in. hold high during normal operation. connects to serial prom data in for ram initialization. connect to 3.3v if unused. trstb/rro i active low reset for jtag/ram init. reset out. hold low during normal operation. connects to serial prom reset for ram initialization. connect to gnd if unused tms i test mode select for jtag. hold high during normal operation. connect to 3.3v if not used for jtag. tck i test clock for jtag. hold high or low during normal operation. connect to 3.3v or gnd if not used for jtag. tdo/rco o test data out for jtag/ram init. clock out. connect to serial prom clock for ram initialization. must be left unconnected if not used for jtag or ram initialization timer interface signals tm_overflow o timer overflow. when timer #1 is in pwm mode, it counts up to 0xffff and then back down to zero. this pwm output signal is a sserted high when the value of the counter is less than or equal to the value programmed in timer #1?s interval register. conversely, this signal is asserted low when the counter is greater than the interval value. tm_enable i timer enable. this signal can be used to enable the timers internal to the quickmips device. internal timer setup registers determine how this signal is used by each timer block. miscellaneous signals cpu_boot(1:0) i boot memory size. these signals indicate to the quickmips device the width of the boot memory (the width of the me mory device connected to cs_n(7)). cpu_boot(1:0) = 00: 8-bit width cpu_boot(1:0) = 01: 16-bit width cpu_boot(1:0) = 10: 32-bit width cpu_boot(1:0) = 11: reserved cpu_bigendian i endian setting. a high on this input indicates big-endian byte ordering; a low on this input indicates little-endian byte ordering. cpu_extint_n(6:0) i cpu interrupts. asserting low any of these inputs causes an interrupt to the quickmips chip. these inputs are active low, level sensit ive, and must be held low for at least two cpu pipeline clocks for the cpu to recognize the interrupt. cpu_extint_n(6) is a non maskable interrupt (nmi). connect to 3.3 v if unused. table 50: pin descriptions (continued) pin i/o function
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 88 stm i quicklogic reserved pin. tie to gnd on the pcb. cpu_reset_n i active low cpu reset. asserting this signal low resets the entire assp portion of the quickmips device (except for the pci contro ller, which has its own reset input). when low, cpu_reset_n causes a cold reset e xception to the mips cpu and halts all internal system clocks. this signal should be asserted for at least five cpu_pll_clkin clock cycles. for reliable operation, the power supply must be stable and the clock must be running before this signal is deasserted. cpu_warmreset_n i active low cpu warm reset. asserting this signal low resets the entire assp portion of the quickmips device (except for the pci controller, which has its own reset input). when low, cpu_warmreset_n causes a warm reset exception to the mips cpu, but all system clocks continue to operate. this signal should be asserted for at least five cpu_pll_clkin clock cycles. for reliable oper ation, the power supp ly must be stable and the clock must be running before this signal is deasserted. fabric pll signals fb_pll_clkin i fabric pll input clock signal. this is the input reference clock to the fabric pll circuit. connect to gnd if the fabric pll is not used. fb_pll_reset_n i fabric pll active low reset. if fb_pll_reset_n is low, then all p ll outputs are reset to zero. connect to gnd if the fabric pll is not used. fb_pll_padout o fabric pll output off chip. this is the pll output clock driven off chip. this output runs at the pll vco (f vco ) frequency determined by the m(1:0) input. leave unconnected if unused. assp pll signals cpu_pll_clkin i input clock signal. this clock input is the reference clock used by the cpu pll. the frequency of the clock on this input is multiplied by eight to drive the mips cpu. cpu_pll_enable_n i active low pll enable signal. this signal must be low to enable the assp-side pll. if cpu_pll_enable_n is held high and cpu_pll_bypass is held low, the ql902m is put into a power saving quiescent state. cpu_pll_bypass i pll bypass. when high, the 8x multiplication of the input clock is not performed and the output clocks are equal to the input frequency. cpu_pll_clkout o output clock signal from the pll. this output operates at the same frequency that is driven to the mips cpu. leave unconnected if unused. cpu_pll_lock o pll lock. the lock output indicates when the pll is locked to the input clock and is producing valid output clocks. leave unconnected if unused. cpu_pll_div(1:0) i system bus clock to mips cpu clock ratio control. see table 2 for more details. table 50: pin descriptions (continued) pin i/o function
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 89 power and ground signals gnd i ground pin. tie to gnd on the pcb. vccio(a:d) i voltage supply pin for each of the four i/o banks. this pin provides the flexibility for the fabric to interface with either a 1.8 v, 2.5 v, or 3.3 v device. every i/o pin in the respective bank is tolerant of vccio(a: d) input signals and out puts vccio(a:d) level signals. this pin must be connected to either 1.8 v, 2.5 v, or 3.3 v. vcc i supply pin. tie to 1.95 v supply. v3v i supply pin. tie to 3.3 v supply. gnd_fb_pll i fabric pll ground pin. tie to analog gnd on the pcb. v3v_fb_pll i fabric pll 3.3 v supply pin. tie to 3.3 v analog supply. gnd_cpu_pll i cpu pll ground pin. tie to analog gnd on the pcb. v3v_cpu_pll i cpu pll 3.3 v supply pin. tie to 3.3 v analog supply. table 50: pin descriptions (continued) pin i/o function
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 90 assp fabric port descriptions table 51: assp to fabric port descriptions port i/o a function ethernet controller signals m1_col, m2_col i ethernet collision detected. the external ethernet phy controller chip asserts col high upon detection of a collision on the medium. col remains asserted while the collision condition persists. the transitions on the col signal are not synchronous to either the txclk or the rxclk. the quickmips mac core ignores the col signal when operating in the full- duplex mode. m1_crs, m2_crs i ethernet carrier sense. the external ethernet phy controller chip asserts crs high when either transmit or receive m edium is non-idle. the phy deasserts crs low when both the transmit and receive medium are idle. the phy must ensure that crs remains asserted throughout the duration of a collision condition. the transitions on the crs signal are not synchronous to either the txclk or the rxclk. m1_mdc, m2_mdc o ethernet management data clock. mdc is sourced by the mac core to the ethernet phy controller as the timing reference for transfer of information on the mdi/mdo signals. mdc is an aperiodic signal that has no maximum high or low times. the minimum high and low times for mdc are 160 ns each, and the minimum period for mdc is 400 ns, regardless of the nominal period of txclk and rxclk. m1_mdi, m2_mdi i ethernet management data in. this is the data input signal from the ethernet phy controller. the phy drives the read data synchronously with respect to the mdc clock during the read cycles. m1_mdo, m2_mdo o ethernet management data out. this is the data output signal from the mac core that drives the control information during the read/write cycles to the external phy controller. the mac core drives the mdo signal synchronously with respect to the mdc. m1_mdo_en_n, m2_mdo_en_n o ethernet management data output enable. this signal, when low, enables the fabric io driver to drive mn_mdo off chip. m1_rxd(3:0), m2_rxd(3:0) i ethernet receive data. rxd(3:0) transition synch ronously with respect to rxclk. the ethernet phy controller chip drives rxd(3:0). for each rxclk period in which rxdv is asserted, rxd(3:0) transfer four bits of recovered data from the phy to the mac core. rxd0 is the least-significant bit. while rxdv is deasserted low, rxd(3:0) has no effect on the mac core. m1_rxdv, m2_rxdv i ethernet receive data valid. the ethernet phy controller asserts rxdv high to indicate to the mac core that it is presenting the recovered and decoded data bits on rxd(3:0) and that the data on rx d(3:0) is synchronous to rxclk. rxdv transitions synchronously with respect to rxclk. rxdv remains asserted continuously from the first recovered nibble of the frame through the final recovered nibble, and is deasserted low prior to the first rxclk that follows the final nibble.
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 91 m1_rxer, m2_rxer i ethernet receive error. the ethernet phy controller chip asserts rxer high for one or more rxclk periods to indicate to the mac core that an error (a coding error or any error that the phy is c apable of detecting that is otherwise undetectable by the mac) was detected somewhere in the frame presently being transferred from the phy to the mac core. rxer transitions synchronously with respect to rxclk. while rxdv is deasserted low, rxer has no effect on the mac core. m1_txd(3:0), m2_txd(3:0) o ethernet transmit data. the quickmips mac core drives txd(3:0). txd(3:0) transition synchronously with respect to txclk. for each txclk period in which txen is asserted, txd(3:0) have the data to be accepted by the ethernet phy controller chip. txd0 is the least-significa nt bit. while txen is deasserted, ignore the data presented on txd(3:0). m1_txen, m2_txen o ethernet transmit enable. a high assertion on txen indicates that the mac core is presenting nibbles on the mii for transmission. the quickmips mac core asserts txen with the first nibble of the preamble and holds txen asserted while all nibbles to be transmitted are presented to the mii. txen is deasserted low prior to the first txclk following the final nibb le of the frame. txen is transitions synchronously with respect to txclk. on-chip system sram block 1 signals sr1_addr(11:2) i on-chip sram block 1 address. this 10-bit address is the memory address for block 1 of the on-chip sram. sr1_clk i on-chip sram block 1 clock. this clock drives block 1 of the on-chip sram. when sram block 1 is connected to the fabric, all sram block 1 io signals are synchronous with this clock. sr1_rdata(31:0) o on-chip sram block 1 read data. this 32-bit bus is the read data from on- chip sram block 1. sr1_wdata(31:0) i on-chip sram block 1 write data. this 32-bit bus is the write data to on-chip sram block 1. sr1_wen i on-chip sram block 1 write enable. this is the active-low write enable to on- chip sram block 1. sr1_wenb(3:0) i on-chip sram block 1 byte write enable. these control signals act as active low byte write enables to on-chip sram block 1. during a write operation, if a bit of sr1_wenb is low, the corresponding data byte on the sr1_wdata bus is written to the sram: sr1_wenb(3) enables sr1_wdata(31:24) sr1_wenb(2) enables sr1_wdata(23:16) sr1_wenb(1) enables sr1_wdata(15:8) sr1_wenb(0) enables sr1_wdata(7:0) on-chip system sram block 2 signals sr2_addr(11:2) i on-chip sram block 2 address. this 10-bit address is the memory address for block 2 of the on-chip sram. sr2_clk i on-chip sram block 2 clock. this clock drives block 2 of the on-chip sram. when sram block 2 is connected to the fabric, all sram block 2 io signals are synchronous with this clock. sr2_rdata(31:0) o on-chip sram block 2 read data. this 32-bit bus is the read data from on- chip sram block 2. table 51: assp to fabric port descriptions (continued) port i/o a function
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 92 sr2_wdata(31:0) i on-chip sram block 2 write data. this 32-bit bus is the write data to on-chip sram block 2. sr2_wen i on-chip sram block 2 write enable. this is the active-low write enable to on- chip sram block 2. sr2_wenb(3:0) i on-chip sram block 2 byte write enable. these control signals act as active low byte write enables to on-chip sram block 2. during a write operation, if a bit of sr2_wenb is low, the corresponding data byte on the sr2_wdata bus is written to the sram: sr2_wenb(3) enables sr2_wdata(31:24) sr2_wenb(2) enables sr2_wdata(23:16) sr2_wenb(1) enables sr2_wdata(15:8) sr2_wenb(0) enables sr2_wdata(7:0) on-chip system sram block 3 signals sr3_addr(11:2) i on-chip sram block 3 address. this 10-bit address is the memory address for block 3 of the on-chip sram. sr3_clk i on-chip sram block 3 clock. this clock drives block 3 of the on-chip sram. when sram block 3 is connected to the fabric, all sram block 3 io signals are synchronous with this clock. sr3_rdata(31:0) o on-chip sram block 3 read data. this 32-bit bus is the read data from on- chip sram block 3. sr3_wdata(31:0) i on-chip sram block 3 write data. this 32-bit bus is the write data to on-chip sram block 3. sr3_wen i on-chip sram block 3 write enable. this is the active-low write enable to on- chip sram block 3. sr3_wenb(3:0) i on-chip sram block 3 byte write enable. these control signals act as active low byte write enables to on-chip sram block 3. during a write operation, if a bit of sr3_wenb is low, the corresponding data byte on the sr3_wdata bus is written to the sram: sr3_wenb(3) enables sr3_wdata(31:24) sr3_wenb(2) enables sr3_wdata(23:16) sr3_wenb(1) enables sr3_wdata(15:8) sr3_wenb(0) enables sr3_wdata(7:0) on-chip system sram block 4 signals sr4_addr(11:2) i on-chip sram block 4 address. this 10-bit address is the memory address for block 4 of the on-chip sram. sr4_clk i on-chip sram block 4 clock. this clock drives block 4 of the on-chip sram. when sram block 4 is connected to the fabric, all sram block 4 io signals are synchronous with this clock. sr4_rdata(31:0) o on-chip sram block 4 read data. this 32-bit bus is the read data from on- chip sram block 4. sr4_wdata(31:0) i on-chip sram block 4 write data. this 32-bit bus is the write data to on-chip sram block 4. sr4_wen i on-chip sram block 4 write enable. this is the active-low write enable to on- chip sram block 4. table 51: assp to fabric port descriptions (continued) port i/o a function
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 93 sr4_wenb(3:0) i on-chip sram block 4 byte write enable. these control signals act as active low byte write enables to on-chip sram block 4. during a write operation, if a bit of sr4_wenb is low, the corresponding data byte on the sr4_wdata bus is written to the sram: sr4_wenb(3) enables sr4_wdata(31:24) sr4_wenb(2) enables sr4_wdata(23:16) sr4_wenb(1) enables sr4_wdata(15:8) sr4_wenb(0) enables sr4_wdata(7:0) ahb and apb clock and reset signals hclk o amba bus clock. all amba bus transactions are synchronous with this clock. upon entering the fabric, hclk is automatically placed on a global clock net. hclk can be programmed to be 1/2, 1/ 3 or 1/4 the cpu clock rate. see table 2 for more details. hresetn o amba bus reset. when low, this signal indicates to the programmable fabric that the assp side of the device is in t he reset state. this signal should be used to reset the fabric ahb master, ahb slave or apb slave interfaces. ahb master and ahb slave interface signals ahb_hready_in o ahb ready input. this signal is used by an ahb master and /or an ahb slave implemented in the fabric. for an ahb master implemented in the fabric: when high, this signal indicates to the ahb master that the accessed ahb sl ave is ready to continue the current transfer. for an ahb slave implemented in the fabric: an ahb slave must only sample the address and control signals and ahbs _hsel when ahb_hready_in is high, indicating that the current transfer is comp leting. under certain circumstances it is possible that ahbs_hsel will be asserted when ahb_hready_in is low, but the selected slave will have changed by the time the current transfer completes. ahb master interface signals ahbm_haddr(31:0) i ahb master address. this bus contains the ahb address for the transfer initiated by the fabric ahb master. ahbm_hburst(2:0) i ahb master burst type. these signals indicate the length of the fabric ahb master burst transfer. possible burst sizes are: 000: single 001: incr (length unspecified) 010: wrap4 011: incr4 100: wrap8 101: incr8 110: wrap16 111: incr16 ahbm_hbusreq i ahb master bus request. when high, this signal indicates to the ahb arbiter that the ahb master implemented in the fabric is requesting ownership of the ahb. ahbm_hgrant o ahb master grant. when high, this signal indicates that the ahb master implemented in the fabric is the current ahb master. table 51: assp to fabric port descriptions (continued) port i/o a function
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 94 ahbm_hprot(3:0) i ahb master protection. protected transfers are not supported by the quickmips device. the ahb master implemented in the fabric should tie all bits of this bus low. ahbm_hrdata(31:0) o ahb master read data. the ahb master implemented in the fabric receives data for ahb reads on this bus. data is received from the selected ahb slave. ahbm_hresp(1:0) o ahb master transfer response. the ahb master implemented in the fabric receives these signals from the accessed ahb slave. for a given transfer, the slave may respond with: 00: okay 01: error 10: retry 11: split (not supported in quickmips) ahbm_hsize(2:0) i ahb master transfer size. the ahb master implement ed in the fabric drives these signals to indicate to the selected slave the size of the transfer taking place. possible transfer sizes are: 000: 8 bits (byte) 001: 16 bits (halfword) 010: 32 bits (word) 011: 64 bits 100: 128 bits (4-word line) 101: 256 bits (8-word line) 110: 512 bits 111: 1024 bits ahbm_htrans(1:0) i ahb master transfer type. the ahb master implemented in the fabric drives these signals to indicate to the selected slave the type of transfer taking place. possible transfer types are: 00: idle 01: busy 10: nonsequential 11: sequential ahbm_hwdata(31:0) i ahb master write data. the ahb master implemented in the fabric drives data for ahb writes on this bus. data is received by the selected ahb slave. ahbm_hwrite i ahb master write. the ahb master implemented in the fabric drives this signal high during an ahb write operation and low during an ahb read. ahb slave interface signals ahbs_haddr(31:0) o ahb slave address. this bus contains the ahb address for the transfer intended for the ahb fabric slave. ahbs_hburst(2:0) o ahb slave burst type. these signals indicate the length of the transfer intended for the ahb fabric slave. possible burst sizes are: 000: single 001: incr (length unspecified) 010: wrap4 011: incr4 100: wrap8 101: incr8 110: wrap16 111: incr16 ahbs_hprot(3:0) o ahb slave protection. protected transfers are not supported by the quickmips device. the ahb slave implemented in the fabric ignores these signals. table 51: assp to fabric port descriptions (continued) port i/o a function
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 95 ahbs_hrdata;(31:0) i ahb slave read data. the ahb slave implemented in the fabric drives data for ahb reads on this bus. data is received by the initiating ahb master. ahbs_hready_out i ahb slave ready output. when high, this signal indicates to the initiating ahb master that the ahb slave implemented in the fabric is ready to continue the current transfer. ahbs_hresp(1:0) i ahb slave transfer response. the initiating ahb master receives these signals from the ahb slave implemented in the fabric. for a given transfer, the slave responds with: 00: okay 01: error 10: retry 11: split (not supported in quickmips) ahbs_hsel o ahb slave select. when high, this signal indicates to the ahb slave implemented in the fabric that it is the selected slave for the current ahb transfer. ahbs_hsize(2:0) o ahb slave transfer size. these signals indicate the size of the transfer intended for the ahb fabric slave. possible transfer sizes are: 000: 8 bits (byte) 001: 16 bits (halfword) 010: 32 bits (word) 011: 64 bits 100: 128 bits (4-word line) 101: 256 bits (8-word line) 110: 512 bits ahbs_htrans(1:0) o ahb slave transfer type. these signals indicate the type of transfer intended for the ahb fabric slave. possible transfer types are: 00: idle 01: busy 10: nonsequential 11: sequential ahbs_hwdata(31:0) o ahb slave write data. the initiating ahb master drives data for ahb writes on this bus. data is intended for the ahb slave in the fabric. ahbs_hwrite o ahb slave write. during an ahb transfer, this signal is driven high during a write operation and low during a read. it is received by the ahb slave implemented in the fabric. apb slave interface signals apbs_paddr(15:2) o apb slave address. this bus contains the apb address for the transfer intended for an apb fabric slave. apbs_penable o apb slave enable. this signal, when high, indicates the second phase (data phase) of an apb transfer intended for an apb fabric slave. apbs_prdata0(31:0) i apb slave 0 read data. the apb slave 0 implemented in the fabric drives data for apb reads on this bus. apbs_prdata1(31:0) i apb slave 1 read data. the apb slave 1 implemented in the fabric drives data for apb reads on this bus. apbs_prdata2(31:0) i apb slave 2 read data. the apb slave 2 implemented in the fabric drives data for apb reads on this bus. apbs_psel0 o apb slave 0 select. this signal, when high, indicates that the current transfer is intended for apb slave 0 implemented in the fabric. table 51: assp to fabric port descriptions (continued) port i/o a function
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 96 apbs_psel1 o apb slave 1 select. this signal, when high, indicates that the current transfer is intended for apb slave 1 implemented in the fabric. apbs_psel2 o apb slave 2 select. this signal, when high, indicates that the current transfer is intended for apb slave 2 implemented in the fabric. apbs_pwdata(31:0) o apb slave write data. all apb slaves implem ented in the fabric receive data for apb write transactions from this bus. apbs_pwrite o apb slave write. during an apb transfer, this signal is driven high during a write operation and low during a read. it is received by all apb slaves implemented in the fabric. timer/counter signals tm_extclk1 i timer 1 external clock. this port allows a clock generated in the fabric to drive timer/counter #1. tm_extclk2 i timer 2 external clock. this port allows a clock generated in the fabric to drive timer/counter #2. tm_extclk3 i timer 3 external clock. this port allows a clock generated in the fabric to drive timer/counter #3. tm_extclk4 i timer 4 external clock. this port allows a clock generated in the fabric to drive timer/counter #4. tm_fbenable i timer enable from fabric. this signal, when high, indicates to the timer enable logic that the fabric design has enabled the timer(s). internal timer setup registers determine how this signal is used by each timer block. tm_overflow2 o timer 2 overflow. when timer #2 is in pwm mode, it counts up to 0xffff and then back down to zero. this pwm output signal is asserted high when the value of the counter is less than or equal to the value programmed in timer #2 interval register. conversely, this signal is asserted low when the counter is greater than the interval value. tm_overflow3 o timer 3 overflow. when timer #3 is in pwm mode, it counts up to 0xffff and then back down to zero. this pwm output signal is asserted high when the value of the counter is less than or equal to the value programmed in timer #3 interval register. conversely, this signal is asserted low when the counter is greater than the interval value. tm_overflow4 o timer 4 overflow. when timer #4 is in pwm mode, it counts up to 0xffff and then back down to zero. this pwm output signal is asserted high when the value of the counter is less than or equal to the value programmed in timer #4 interval register. conversely, this signal is asserted low when the counter is greater than the interval value. mips cpu signals fb_bigendian o big endian indicator to fabric. this signal, when high, indicates to the fabric that the quickmips device is in big endian mode. fb_int i interrupt from fabric. this signal, when driven high by a design in the fabric, causes an interrupt to the mips processor. this input is active high and level sensitive. pm_dcachehit o performance monitor data cache hit. this signal is asserted whenever there is a data cache hit. this signal is synchronous with cpu_pll_clkout. pm_dcachemiss o performance monito r data cache miss. this signal is asserted whenever there is a data-cache miss. this signal is synchronous with cpu_pll_clkout. table 51: assp to fabric port descriptions (continued) port i/o a function
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 97 pm_dtlbhit o performance monitor data tlb hit. this signal is asserted whenever there is a hit in the data tlb. this signal is synchronous with cpu_pll_clkout. pm_dtlbmiss o performance monitor data tlb miss. this signal is asserted whenever there is a miss in the data tlb. this signal is synchronous with cpu_pll_clkout. pm_icachehit o performance monitor in struction cache hit. this signal is asserted whenever there is an instruction-cache hit. this signal is synchronous with cpu_pll_clkout. pm_icachemiss o performance monitor instruction cache miss. this signal is asserted whenever there is an instruction-cache miss. this signal is synchronous with cpu_pll_clkout. pm_instncomplete o performance monitor in struction complete. this signal is asserted each time an instruction completes in the pipeline. this signal is synchronous with cpu_pll_clkout. pm_itlbhit o performance monitor instruction tlb hit. this signal is asserted whenever there is an instruction tlb hit. this signal is synchronous with cpu_pll_clkout. pm_itlbmiss o performance monitor instruction tlb miss. this signal is asserted whenever there is an instruction tlb miss. this signal is synchronous with cpu_pll_clkout. pm_jtlbhit o performance monitor joint tlb hit. this signal is asserted whenever there is a joint tlb hit. this signal is synchronous with cpu_pll_clkout. pm_jtlbmiss o performance monitor joint tlb miss. this signal is asserted whenever there is a joint tlb miss. this signal is synchronous with cpu_pll_clkout. pm_wtbmerge o performance monitor write-through merge. this signal is asserted whenever there is a successful merge in the write- through buffer. this signal is synchronous with cpu_pll_clkout. pm_wtbnomerge o performance monitor write-through non-merge. this signal is asserted whenever a non-merging store is written to the write-through buffer. this signal is synchronous with cpu_pll_clkout. si_rp o reduce power indicator to fabric. this signal represents the state of the rp bit (27) in the mips cp0 status register. softw are can write this bit to indicate that the device can enter a reduced power mode. this signal is synchronous with cpu_pll_clkout. si_sleep o sleep indicator to fabric. this signal is asserted by the mips core whenever the wait instruction is executed. the assertio n of this signal indicates that the clock has stopped and that the core is waiting for an interrupt. this signal is synchronous with cpu_pll_clkout. cpu pll status io_mips_pll_lock o pll lock indicator. this signal, when high, indicates to the fabric that the assp pll has achieved phase lock on the incoming reference clock signal. table 51: assp to fabric port descriptions (continued) port i/o a function
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 98 pci configuration settings af_pci_cfgdone i pci configuration done. this signal represents the in itial value (after reset) of the config done bit in the pci dma registers. after reset, the value of this register may be overwritten through the ahb. the purpos e for this register is to disable the pci interface until the mips processor is ready. this may be useful when the read- only id registers in the pci configuration space will be over-written by the mips processor, which will require some time. while this register is 0, retries will be signaled on the pci bus, thus signaling that the quickmips device is not ready, and the pci transaction should be tried again at a later time. note that the pci specification limits the length of time t hat a device can retry a transaction, and states the amount of time after the pci reset is deasserted when a pci configuration cycle may occur. in an embedded system, however, a designer may choose to violate certain pci specifications if he/she knows it will not have a detrimental impact on the syst em. this signal is tie-low or tie-high in the fabric only. af_pci_classcode(23:0) i pci class code. these signals represent the initial value (after reset) of the class code bits in the pci configuration register s. after reset, the value of this register may be overwritten through the ahb. the class code register is used to identify the generic function of the device and, in some cases, a specific register-level programming interface. these signals are tie-low or tie-high in the fabric only. af_pci_devid(15:0) i pci device id. these signals represent the initial va lue (after reset) of the device id bits in the pci configuration registers. after reset, the value of this register may be overwritten through the ahb. this field identifies the particular pci device. this identifier is allocated by the vendor. these signals are tie-low or tie-high in the fabric only. af_pci_host i pci host. this signal represents the initial val ue (after reset) of the host mode bit in the pci dma registers. after reset, the value of this register may be overwritten through the ahb. this regist er controls whether the quic kmips device acts as the pci system host or is a satellite device. a system host must configure itself as well as all the devices on the pci bus, whereas a satellite device will be configured by another device (the host) of the pci system. note that while in host mode, the pci configuration registers may only be accessed by the ahb, but while in satellite (non-host) mode, the pci configuration r egisters may only be accessed by the pci bus. this signal is tie-low or tie-high in the fabric only. af_pci_maxlat(7:0) i pci maximum latency. these signals represent the initial value (after reset) of the max latency bits in the pci configuratio n registers. after reset, the value of this register may be overwritten throug h the ahb. this register is used for specifying how often the device needs to gain access to pci bus. these signals are tie-low or tie-high in the fabric only. af_pci_mingnt(7:0) i pci minimum grant. these signals represent the init ial value (after reset) of the min grant bits in the pci configuration r egisters. after reset, the value of this register may be overwritten through the ahb. this register is used for specifying how long a burst period the device needs assuming a clock rate of 33 mhz.these signals are tie-low or tie-high in the fabric only. af_pci_revid(7:0) i pci revision id. these signals represent the initia l value (after reset) of the revision id bits in the pci configuration r egisters. after reset, the value of this register may be overwritten through the ah b. this register specifies a device specific revision identifier. the value is chosen by the vendor (zero is an acceptable value). this field should be viewed as a vendor defined extension to the device id. these signals are tie-low or tie-high in the fabric only. table 51: assp to fabric port descriptions (continued) port i/o a function
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 99 af_pci_subsysid(15:0) i pci subsystem id. these signals represent the initial value (after reset) of the subsystem id bits in the pci configuration registers. after reset, the value of this register may be overwritten through the ahb. these registers are used to uniquely identify the expansion board or subsystem where the pci device resides. they provide a mechanism for expansion board vendors to distinguish their boards from one another even though the boards may ha ve the same pci controller on them. these signals are tie-low or tie-high in the fabric only. af_pci_subsysvid(15:0) i pci subsystem vendor id. these signals represent the initial value (after reset) of the subsystem vendor id bits in the pc i configuration regist ers. after reset, the value of this register may be overwritten through the ahb. these registers are used to uniquely identify the expansion bo ard or subsystem where the pci device resides. they provide a mechanism for expansion board vendors to distinguish their boards from one another even though the boards may have the same pci controller on them. these signals are tie-low or tie-high in the fabric only. af_pci_venid(15:0) i pci vendor id. these signals represent the initial value (after reset) of the vendor id bits in the pci configuration registers. after reset, the value of this register may be overwritten through the ahb. this field identifies the ma nufacturer of the device. valid vendor identifiers are allocated by the pci sig to ensure uniqueness. these signals are tie-low or tie-high in the fabric only. a. interface direction is s pecified with respect to the assp portion of the device. i desig nates an input to the assp and o designates an output from the assp. table 51: assp to fabric port descriptions (continued) port i/o a function
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 100 544 bga pinout table table 52: 544 bga pinout table ball function ball function ball function ball function ball function a1 gnd c1 i/o(d) e1 i/o(d) g1 i/o(d) k23 i/o(a) a2 i/o(d) c2 vccio(d) e2 i/o(d) g2 i/o(d) k24 i/o(a) a3 i/o(d) c3 i/o(d) e3 i/o(d) g3 i/o(d) k25 gnd a4 i/o(c) c4 i/o(d) e4 ioctrl(d) g4 i/o(c) k26 gnd a5 i/o(c) c5 vccio(c) e5 i/o(d) g5 i/o(c) l1 tck a6 i/o(c) c6 i/o(c) e6 i/o(c) g6 gnd l2 clk(0) a7 inref(c) c7 i/o(c) e7 i/o(c) g21 vcc l3 i/o(d) a8 i/o(c) c8 ioctrl(c) e8 i/o(c) g22 i/o(b) l4 i/o(d) a9 vccio(c) c9 ioctrl(c) e9 i/o(c) g23 i/o(b) l5 i/o(d) a10 i/o(c) c10 i/o(c) e10 i/o(c) g24 i/o(b) l6 vccio(d) a11 i/o(c) c11 i/o(c) e11 i/o(c) g25 i/o(a) l10 gnd a12 vccio(c) c12 i/o(c) e12 i/o(c) g26 i/o(a) l11 gnd a13 clk(8) c13 i/o(b) e13 i/o(c) h1 i/o(d) l12 gnd a14 clk(5) c14 clk(7) e14 i/o(b) h2 i/o(d) l13 gnd a15 i/o(b) c15 i/o(b) e15 i/o(b) h3 v3v l14 gnd a16 i/o(b) c16 i/o(b) e16 i/o(b) h4 gnd l15 gnd a17 i/o(b) c17 inref(b) e17 i/o(b) h5 i/o(c) l16 gnd a18 i/o(b) c18 ioctrl(b) e18 i/o(b) h6 vcc l17 gnd a19 ioctrl(b) c19 i/o(b) e19 i/o(b) h21 gnd l21 vccio(a) a20 i/o(b) c20 i/o(b) e20 i/o(b) h22 v3v l22 i/o(a) a21 i/o(b) c21 i/o(b) e21 i/o(b) h23 i/o(b) l23 i/o(a) a22 i/o(a) c22 gnd e22 i/o(b) h24 vccio(a) l24 i/o(a) a23 i/o(a) c23 i/o(a) e23 i/o(b) h25 i/o(a) l25 v3v a24 vccio(b) c24 i/o(a) e24 i/o(a) h26 dedclk/clk(4) l26 gnd a25 ioctrl(a) c25 i/o(a) e25 i/o(a) j1 i/o(d) m1 gnd a26 gnd c26 i/o(a) e26 i/o(a) j2 gnd m2 tdi b1 i/o(d) d1 i/o(d) f1 i/o(d) j3 vccio(d) m3 i/o(d) b2 i/o(c) d2 i/o(d) f2 i/o(d) j4 i/o(c) m4 i/o(d) b3 i/o(c) d3 gnd f3 i/o(d) j5 i/o(c) m5 i/o(d) b4 i/o(c) d4 ioctrl(d) f4 inref(d) j6 vccio(d) m6 vccio(d) b5 i/o(c) d5 i/o(d) f5 i/o(d)) j21 vccio(a) m10 gnd b6 i/o(c) d6 i/o(c) f6 i/o(c) j22 i/o(a) m11 gnd b7 gnd d7 i/o(c) f7 vcc j23 i/o(b) m12 gnd b8 i/o(c) d8 i/o(c) f8 vcc j24 i/o(b) m13 gnd b9 i/o(c) d9 i/o(c) f9 vccio(c) j25 clk(3) m14 gnd b10 i/o(c) d10 i/o(c) f10 vccio(c) j26 clk(2) m15 gnd b11 i/o(c) d11 i/o(c) f11 vccio(c) k1 i/o(d) m16 gnd b12 tms d12 i/o(c) f12 gnd k2 i/o(d) m17 gnd b13 gnd d13 io(c) f13 vcc k3 i/o(d) m21 gnd b14 clk(6) d14 i/o(b) f14 vcc k4 i/o(d) m22 i/o(a) b15 i/o(b) d15 i/o(b) f15 gnd k5 i/o(d) m23 i/o(a) b16 i/o(b) d16 i/o(b) f16 vccio(b) k6 vccio(d) m24 i/o(a) b17 vccio(b) d17 i/o(b) f17 vccio(b) k10 gnd m25 trstb b18 gnd d18 i/o(b) f18 vccio(b) k11 gnd m26 nc b19 i/o(b) d19 i/o(b) f19 vcc k12 gnd n1 stm b20 i/o(b) d20 i/o(b) f20 gnd k13 gnd n2 tdo b21 vccio(b) d21 i/o(b) f21 vcc k14 gnd n3 v3v b22 i/o(a) d22 i/o(b) f22 i/o(b) k15 gnd n4 clk(1) b23 i/o(a) d23 i/o(a) f23 i/o(a) k16 gnd n5 v3v b24 inref(a) d24 gnd f24 i/o(a) k17 gnd n6 gnd b25 ioctrl(a) d25 vccio(a) f25 i/o(a) k21 vccio(a) n10 gnd b26 i/o(a) d26 i/o(a) f26 i/o(a) k22 i/o(a) n11 gnd
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 101 n12 gnd t1 m1_txclk w1 pci_rst_n ab3 pci_ad(22) ad3 pci_ad(12) n13 gnd t2 m1_rxclk w2 tm_overflow ab4 pci_ad(24) ad4 pci_ad(13) n14 gnd t3 cpu_pll_div(1) w3 v3v ab5 pci_ad(18) ad5 pci_ad(5) n15 gnd t4 tm_enable w4 pci_ad(23) ab6 pci_c_be_n(3) ad6 pci_perr_n n16 gnd t5 nc w5 pci_ad(17) ab7 pci_stop_n ad7 pci_c_be_n(2) n17 gnd t6 cpu_pll_clkin w6 v3v ab8 pci_trdy_n ad8 pci_devsel_n n21 vcc t10 gnd w21 v3v ab9 pci_serr_n ad9 pci_ad(15) n22 i/o(a) t11 gnd w22 sd_clkin ab10 pci_ad(0) ad10 pci_ad(4) n23 i/o(a) t12 gnd w23 addr(9) ab11 ejtag_tms ad11 pci_ad(1) n24 i/o(a) t13 gnd w24 v3v ab12 u1_dsr_n ad12 ejtag_tdo n25 m2_txclk t14 gnd w25 bls_n(2) ab13 u1_cts_n ad13 ejtag_tdi n26 m2_rxclk t15 gnd w26 addr(0) ab14 sd_cs_n(0) ad14 u1_rxd_sirin p1 cpu_pll_bypass t16 gnd y1 pci_ad(30) ab15 data(26) ad15 sd_dqm(3) p2 cpu_pll_enable_n t17 gnd y2 pci_idsel ab16 data(15) ad16 data(24) p3 vccio(d) t21 gnd_fb_pll y3 pci_gnt_n ab17 data(4) ad17 data(14) p4 cpu_reset_n t22 cs_n(1) y4 pci_ad(29) ab18 addr(17) ad18 addr(18) p5 v3v_cpu_pll t23 ejtag_debugm y5 pci_ad(16) ab19 addr(19) ad19 addr(23) p6 vcc t24 cs_n(4) y6 vcc ab20 addr(20) ad20 addr(14) p10 gnd t25 gnd y21 gnd ab21 addr(22) ad21 data(25) p11 gnd t26 cs_n(5) y22 addr(13) ab22 data(0) ad22 data(23) p12 gnd u1 cpu_boot(1) y23 addr(2) ab23 data(1) ad23 data(16) p13 gnd u2 gnd y24 addr(3) ab24 data(2) ad24 data(13) p14 gnd u3 cpu_boot(0) y25 addr(4) ab25 data(3) ad25 gnd p15 gnd u4 pci_inta_n y26 addr(6) ab26 data(5) ad26 data(12) p16 gnd u5 pci_req_n aa1 pci_ad(25) ac1 pci_ad(14) ae1 pci_ad(9) p17 gnd u6 gnd_cpu_pll aa2 pci_ad(26) ac2 v3v ae2 pci_ad(7) p21 vcc u10 gnd aa3 pci_ad(28) ac3 gnd ae3 pci_ad(3) p22 v3v_fb_pll u11 gnd aa4 pci_ad(19) ac4 pci_c_be_n(0) ae4 gnd p23 v3v u12 gnd aa5 pci_clk ac5 v3v ae5 cpu_extint_n(6) p24 vccio(a) u13 gnd aa6 gnd ac6 pci_par ae6 cpu_extint_n(3) p25 nc u14 gnd aa7 gnd ac7 pci_irdy_n ae7 gnd p26 ejtag_dint u15 gnd aa8 v3v ac8 pci_frame_n ae8 ejtag_tck r1 cpu_pll_div(0) u16 gnd aa9 v3v ac9 v3v ae9 v3v r2 cpu_pll_lock u17 gnd aa10 v3v ac10 pci_ad(8) ae10 u1_rts_n r3 cpu_pll_clkout u21 v3v aa11 gnd ac11 cpu_extint_n(5) ae11 gnd r4 nc u22 oe_n aa12 gnd ac12 u2_txd_sirout ae12 u1_dcd_n r5 cpu_warmreset_n u23 bls_n(3) aa13 vcc ac13 u2_rxd_sirin ae13 v3v r6 vcc u24 we_n aa14 v3v ac14 sd_ras_n ae14 sd_cke(1) r10 gnd u25 cs_n(6) aa15 v3v ac15 data(30) ae15 sd_we_n r11 gnd u26 cs_n(7) aa16 gnd ac16 data(19) ae16 nc r12 gnd v1 gnd aa17 vcc ac17 data(8) ae17 v3v r13 gnd v2 gnd aa18 v3v ac18 addr(21) ae18 gnd r14 gnd v3 pci_ad(27) aa19 v3v ac19 addr(16) ae19 sd_clkout r15 gnd v4 pci_ad(31) aa20 gnd ac20 addr(15) ae20 v3v r16 gnd v5 pci_ad(20) aa21 vcc ac21 data(6) ae21 data(31) r17 gnd v6 gnd aa22 addr(12) ac22 data(7) ae22 data(29) r21 fb_pll_clkin v21 v3v aa23 addr(7) ac23 data(9) ae23 v3v r22 fb_pll_padout v22 addr(8) aa24 gnd ac24 data(10) ae24 data(20) r23 fb_pll_reset_n v23 addr(5) aa25 addr(10) ac25 v3v ae25 data(18) r24 cs_n(0) v24 addr(1) aa26 addr(11) ac26 data(11) ae26 data(17) r25 cs_n(2) v25 bls_n(0) ab1 pci_c_be_n(1) ad1 pci_ad(10) af1 gnd r26 cs_n(3) v26 bls_n(1) ab2 pci_ad(21) ad2 pci_ad(11) af2 pci_ad(6) table 52: 544 bga pinout table (continued) ball function ball function ball function ball function ball function
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 102 af3 pci_ad(2) af8 cpu_extint_n(0) af13 nc af18 sd_cs_n(1) af23 data(27) af4 ejtag_trst_n af9 cpu_bigendian af14 nc af19 sd_dqm(2) af24 data(22) af5 cpu_extint_n(4) af10 u1_dtr_n af15 sd_cke(0) af20 sd_dqm(1) af25 data(21) af6 cpu_extint_n(2) af11 u1_ri_n af16 sd_cas_n af21 sd_dqm(0) af26 gnd af7 cpu_extint_n(1) af12 u1_txd_sirout af17 nc af22 data(28) table 52: 544 bga pinout table (continued) ball function ball function ball function ball function ball function
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 103 544 bga pinout drawing figure 57: 544 bga pinout diagram
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 104 ordering information contact information phone: (408) 990-4000 (us) (905) 940-4149 (canada) +(44) 1932 57 9011 (europe ? except german y/benelux) +(49) 89 930 86 170 (germany/benelux) +(86) 21 6867 0273 (asia ? except japan) +(81) 45 470 5525 (japan) e-mail: info@quicklogic.com sales: www.quicklogic.com/sales support: www.quicklogic.com/support internet: www.quicklogic.com ql 902m -1 ps544 c operating range: c = commercial i = industrial package lead count: ps544 (psn544)* = 544-ball bga (1.0 mm) 902m part number: quicklogic device fabric speed: -1 fast -2 faster 175 processor speed: 175 mhz 200 mhz * lead-free packaging is available, contact quicklogic regarding availability (see contact information) .
? 2005 quicklogic corporation www.quicklogic.com ql902m quickmips? data sheet rev. i preliminary 105 revision history revision date comments a may 2003 judd heape and kathleen murchek b june 2003 judd heape and kathleen murchek modifications to all sections including pinout tables and ac timing parameters. added section related to operation of on-chip sram. c june 2003 judd heape and kathleen murchek modifications to all sections including pinout tables and ac timing parameters. added interrupt controller section. d july 2003 judd heape and kathleen murchek general clean-up of document text and figures. added ecu and dual-port ram signals. added text to assp i/o dc charac teristics and assp to fabric interface output timing tables. added new section - board layout recommendations. replaced advanced clocks network section. e july 2003 judd heape and kathleen murchek new pll power supply filtering illustration and general clean-up of document text. modified multiple i/o banks figure. f december 2003 judd heape and kathleen murchek changed t jmax number from 150c to 125c in package thermal characteristics section. added i cc(static) row to dc characteristics table. added an ahb master and ahb slave interface signals section with an ahb_hready_in row to assp to fabric port descriptions table. changed v cc supply specification to 1.95 0.05 v. g march 2004 judd heape and kathleen murchek removed fabric ram modes 512x4 and 1024x2. updated ac and dc characteristics including all fabric timing and assp to fabric interface timing. added fabric pll timing data and modified clock network figures. added system sram timing data and added timing diagrams. modified power-up sequencing section. modified security and flexibility fuse descriptions in jtag section. modified ejtag pin descriptions. added fabric i/o voltage and current graphs to dc characteristics section. h september 2004 judd heape and kathleen murchek removed i fab_pll and i cpu_pll sections from dc characteristics table. changed all instances of vcc_fb_pll and vcc_cpu_pll to vcc. removed vcc_fb_pll and vcc_cpu_pll from pin description table and pll power supply filtering circuits figure. removed instances of analog v cc , fb_pll_vcc and cpu_pll_vcc from pll power supply filtering section. updated text and tables in fabric pll signals section i september 2005 ian ferguson and kathleen murchek added lead free packaging information.
www.quicklogic.com ? 2005 quicklogic corporation ql902m quickmips? data sheet rev. i preliminary 106 copyright and trademark information copyright ? 2005 quicklogic corporation. all rights reserved. the information contained in this document and th e accompanying software programs are protected by copyright. all rights are reserved by quicklogic corporation. quicklogic corporation reserves the right to modify this document without any obligation to notif y any person or entity of such revision. copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of quicklogic is prohibited. quicklogic and the quicklogic logo, pa sic, vialink, deskfab, and quickworks are registered trademarks of quicklogic corporation; eclipse, quickfc, qu ickdsp, quickdr, quicksd, quicktools, quickcore, quickpro, spde, webasic, and webesp are trademarks of quicklogic corporation.

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